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-------------------------------------------------------------------------------
-- Title      :  HDLC components package
-- Project    :  HDLC controller
-------------------------------------------------------------------------------
-- File        : hdlc_components_pkg.vhd
-- Author      : Jamil Khatib  (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created     : 2000/12/30
-- Last update: 2001/04/27
-- Platform    : 
-- Simulators  : Modelsim 5.3XE/Windows98
-- Synthesizers: 
-- Target      : 
-- Dependency  : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description:  HDLC components package
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :   30 Dec 2000
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   Created
-- ToOptimize      :
-- Bugs            : 
-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   2
-- Version         :   0.2
-- Date            :   12 Jan 2001
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   RxEnable bug fixed
--
-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   3
-- Version         :   0.3
-- Date            :   16 Jan 2001
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   TX componentes added
--
-------------------------------------------------------------------------------
-- Revision Number :   4
-- Version         :   0.4
-- Date            :   22 March 2001
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   Tx Top components added
--
-------------------------------------------------------------------------------
-- Revision Number :   5
-- Version         :   0.5
-- Date            :   9 April 2001
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   Rx Top components added
--
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.11  2001/04/27 18:21:59  jamil
-- After Prelimenray simulation
--
-- Revision 1.10  2001/04/22 20:08:16  jamil
-- Top level simulation
--
-- Revision 1.7  2001/04/14 15:23:34  jamil
-- Rx Components added
--
-- Revision 1.6  2001/03/22 21:58:46  jamil
-- Top Tx Components added
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
package hdlc_components_pkg is
 
  component hdlc_ent
    generic (
      FCS_TYPE  :     integer;
      ADD_WIDTH :     integer);
    port (
      Txclk     : in  std_logic;
      RxClk     : in  std_logic;
      Tx        : out std_logic;
      Rx        : in  std_logic;
      TxEN      : in  std_logic;
      RxEn      : in  std_logic;
      RST_I     : in  std_logic;
      CLK_I     : in  std_logic;
      ADR_I     : in  std_logic_vector(2 downto 0);
      DAT_O     : out std_logic_vector(31 downto 0);
      DAT_I     : in  std_logic_vector(31 downto 0);
      WE_I      : in  std_logic;
      STB_I     : in  std_logic;
      ACK_O     : out std_logic;
      CYC_I     : in  std_logic;
      RTY_O     : out std_logic;
      TAG0_O    : out std_logic;
      TAG1_O    : out std_logic);
  end component;
 
 
  constant ADD_WIDTH :     integer := 7;  -- Internal Buffers address width
  component WB_IF_ent
    generic (
      ADD_WIDTH      :     integer);
    port (
      CLK_I          : in  std_logic;
      RST_I          : in  std_logic;
      ACK_O          : out std_logic;
      ADR_I          : in  std_logic_vector(2 downto 0);
      CYC_I          : in  std_logic;
      DAT_I          : in  std_logic_vector(31 downto 0);
      DAT_O          : out std_logic_vector(31 downto 0);
      RTY_O          : out std_logic;
      STB_I          : in  std_logic;
      WE_I           : in  std_logic;
      TAG0_O         : out std_logic;
      TAG1_O         : out std_logic;
      TxEnable       : out std_logic;
      TxDone         : in  std_logic;
      TxDataInBuff   : out std_logic_vector(7 downto 0);
      Txwr           : out std_logic;
      TxAborted      : in  std_logic;
      TxAbort        : out std_logic;
      TxOverflow     : in  std_logic;
      TxFCSen        : out std_logic;
      RxFrameSize    : in  std_logic_vector(ADD_WIDTH-1 downto 0);
      RxRdy          : in  std_logic;
      RxDataBuffOut  : in  std_logic_vector(7 downto 0);
      RxOverflow     : in  std_logic;
      RxFrameError   : in  std_logic;
      RxFCSErr       : in  std_logic;
      RxRd           : out std_logic;
      RxAbort        : in  std_logic);
  end component;
 
  component txSynch_ent
    port (
      rst_n           : in  std_logic;
      clk_D1          : in  std_logic;
      clk_D2          : in  std_logic;
      rdy_D1          : in  std_logic;
      rdy_D2          : out std_logic;
      ack             : out std_logic;
      TXD_D1          : out std_logic_vector(7 downto 0);
      TXD_D2          : in  std_logic_vector(7 downto 0);
      ValidFrame_D1   : out std_logic;
      ValidFrame_D2   : in  std_logic;
      AbortedTrans_D1 : in  std_logic;
      AbortedTrans_D2 : out std_logic;
      AbortFrame_D1   : out std_logic;
      AbortFrame_D2   : in  std_logic;
      WriteByte_D1    : out std_logic;
      WriteByte_D2    : in  std_logic);
  end component;
 
  component Txfcs_ent
    generic (
      FCS_TYPE    :     integer);
    port (
      TxClk       : in  std_logic;
      rst_n       : in  std_logic;
      FCSen       : in  std_logic;
      ValidFrame  : out std_logic;
      WriteByte   : out std_logic;
      rdy         : in  std_logic;
      ack         : in  std_logic;
      TxData      : out std_logic_vector(7 downto 0);
      TxDataAvail : in  std_logic;
      RdBuff      : out std_logic;
      TxDataBuff  : in  std_logic_vector(7 downto 0));
  end component;
 
  component TxBuff_ent
    generic (
      ADD_WIDTH     :     integer);
    port (
      TxClk         : in  std_logic;
      rst_n         : in  std_logic;
      RdBuff        : in  std_logic;
      Wr            : in  std_logic;
      TxDataAvail   : out std_logic;
      TxEnable      : in  std_logic;
      TxDone        : out std_logic;
      TxDataOutBuff : out std_logic_vector(7 downto 0);
      TxDataInBuff  : in  std_logic_vector(7 downto 0);
      Full          : out std_logic);
  end component;
 
  component TxChannel_ent
    port (
      TxClk        : in  std_logic;
      rst_n        : in  std_logic;
      TXEN         : in  std_logic;
      Tx           : out std_logic;
      ValidFrame   : in  std_logic;
      AbortFrame   : in  std_logic;
      AbortedTrans : out std_logic;
      WriteByte    : in  std_logic;
      rdy          : out std_logic;
      TxData       : in  std_logic_vector(7 downto 0));
  end component;
 
  component TxCont_ent
    port (
      TXclk         : in  std_logic;
      rst_n         : in  std_logic;
      TXEN          : in  std_logic;
      enable        : out std_logic;
      BackendEnable : out std_logic;
      abortedTrans  : in  std_logic;
      inProgress    : in  std_logic;
      ValidFrame    : in  std_logic;
      Frame         : out std_logic;
      AbortFrame    : in  std_logic;
      AbortTrans    : out std_logic);
  end component;
 
  component flag_ins_ent
    port (
      TXclk      : in  std_logic;
      rst_n      : in  std_logic;
      TX         : out std_logic;
      TXEN       : in  std_logic;
      TXD        : in  std_logic;
      AbortFrame : in  std_logic;
      Frame      : in  std_logic);
  end component;
 
  component ZeroIns_ent
    port (
      TxClk         : in  std_logic;
      rst_n         : in  std_logic;
      enable        : in  std_logic;
      BackendEnable : in  std_logic;
      abortedTrans  : out std_logic;
      inProgress    : out std_logic;
      ValidFrame    : in  std_logic;
      Writebyte     : in  std_logic;
      rdy           : out std_logic;
      TXD           : out std_logic;
      Data          : in  std_logic_vector(7 downto 0));
  end component;
 
  component rxcont_ent
    port (
      RxClk        : in  std_logic;
      rst          : in  std_logic;
      RxEn         : in  std_logic;
      AbortedFrame : out std_logic;
      Abort        : in  std_logic;
      FlagDetect   : in  std_logic;
      ValidFrame   : out std_logic;
      FrameError   : out std_logic;
      aval         : in  std_logic;
      initzero     : out std_logic;
      enable       : out std_logic);
  end component;
 
 
  component ZeroDetect_ent
    port (
      ValidFrame   : in  std_logic;     --New
      Readbyte     : in  std_logic;
      aval         : out std_logic;
      enable       : in  std_logic;
      StartOfFrame : in  std_logic;
      rdy          : out std_logic;
      rst          : in  std_logic;
      RxClk        : in  std_logic;
      RxD          : in  std_logic;
      RxData       : out std_logic_vector(7 downto 0));
  end component;
 
  component FlagDetect_ent
    port (
      Rxclk      : in  std_logic;
      rst        : in  std_logic;
      FlagDetect : out std_logic;
      Abort      : out std_logic;
      RXEN       : in  std_logic;
      RXEN_O     : out std_logic;
      RXD        : out std_logic;
      RX         : in  std_logic);
  end component;
 
  component RxChannel_ent
    port (
      Rxclk       : in  std_logic;
      rst         : in  std_logic;
      Rx          : in  std_logic;
      RxData      : out std_logic_vector(7 downto 0);
      ValidFrame  : out std_logic;
      AbortSignal : out std_logic;
      FrameError  : out std_logic;
      Readbyte    : in  std_logic;
      rdy         : out std_logic;
      RxEn        : in  std_logic);
  end component;
 
  component RxSynch_ent
    port (
      rst_n          : in  std_logic;
      clk_D1         : in  std_logic;
      clk_D2         : in  std_logic;
      rdy_D1         : in  std_logic;
      rdy_D2         : out std_logic;
      RXD_D1         : in  std_logic_vector(7 downto 0);
      RXD_D2         : out std_logic_vector(7 downto 0);
      ValidFrame_D1  : in  std_logic;
      ValidFrame_D2  : out std_logic;
      AbortSignal_D1 : in  std_logic;
      AbortSignal_D2 : out std_logic;
      FrameError_D1  : in  std_logic;
      FrameError_D2  : out std_logic;
      ReadByte_D1    : out std_logic;
      ReadByte_D2    : in  std_logic);
  end component;
 
  component RxFCS_ent
    generic (
      FCS_TYPE   :     integer);
    port (
      clk        : in  std_logic;
      rst_n      : in  std_logic;
      RxD        : in  std_logic_vector(7 downto 0);
      ValidFrame : in  std_logic;
      rdy        : in  std_logic;
      Readbyte   : out std_logic;
      DataBuff   : out std_logic_vector(7 downto 0);
      WrBuff     : out std_logic;
      EOF        : out std_logic;
      FCSen      : in  std_logic;
      FCSerr     : out std_logic);
  end component;
 
  component RxBuff_ent
    generic (
      FCS_TYPE      :     integer;
      ADD_WIDTH     :     integer);
    port (
      Clk           : in  std_logic;
      rst_n         : in  std_logic;
      DataBuff      : in  std_logic_vector(7 downto 0);
      EOF           : in  std_logic;
      WrBuff        : in  std_logic;
      FrameSize     : out std_logic_vector(ADD_WIDTH-1 downto 0);
      RxRdy         : out std_logic;
      RxDataBuffOut : out std_logic_vector(7 downto 0);
      Overflow      : out std_logic;
      Rd            : in  std_logic);
  end component;
 
end hdlc_components_pkg;

Line No.	Rev	Author	Line
1	2	khatib	`-------------------------------------------------------------------------------`
2			`-- Title : HDLC components package`
3			`-- Project : HDLC controller`
4			`-------------------------------------------------------------------------------`
5			`-- File : hdlc_components_pkg.vhd`
6			`-- Author : Jamil Khatib (khatib@ieee.org)`
7			`-- Organization: OpenIPCore Project`
8			`-- Created : 2000/12/30`
9	9	khatib	`-- Last update: 2001/04/27`
10	2	khatib	`-- Platform :`
11			`-- Simulators : Modelsim 5.3XE/Windows98`
12			`-- Synthesizers:`
13			`-- Target :`
14			`-- Dependency : ieee.std_logic_1164`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- Description: HDLC components package`
18			`-------------------------------------------------------------------------------`
19			`-- Copyright (c) 2000 Jamil Khatib`
20			`--`
21			`-- This VHDL design file is an open design; you can redistribute it and/or`
22			`-- modify it and/or implement it after contacting the author`
23			`-- You can check the draft license at`
24			`-- http://www.opencores.org/OIPC/license.shtml`
25
26			`-------------------------------------------------------------------------------`
27			`-- Revisions :`
28			`-- Revision Number : 1`
29			`-- Version : 0.1`
30			`-- Date : 30 Dec 2000`
31			`-- Modifier : Jamil Khatib (khatib@ieee.org)`
32			`-- Desccription : Created`
33			`-- ToOptimize :`
34			`-- Bugs :`
35			`-------------------------------------------------------------------------------`
36	5	khatib	`-- Revisions :`
37			`-- Revision Number : 2`
38			`-- Version : 0.2`
39			`-- Date : 12 Jan 2001`
40			`-- Modifier : Jamil Khatib (khatib@ieee.org)`
41			`-- Desccription : RxEnable bug fixed`
42			`--`
43			`-------------------------------------------------------------------------------`
44	7	khatib	`-- Revisions :`
45			`-- Revision Number : 3`
46			`-- Version : 0.3`
47			`-- Date : 16 Jan 2001`
48			`-- Modifier : Jamil Khatib (khatib@ieee.org)`
49			`-- Desccription : TX componentes added`
50			`--`
51			`-------------------------------------------------------------------------------`
52	9	khatib	`-- Revision Number : 4`
53			`-- Version : 0.4`
54			`-- Date : 22 March 2001`
55			`-- Modifier : Jamil Khatib (khatib@ieee.org)`
56			`-- Desccription : Tx Top components added`
57			`--`
58			`-------------------------------------------------------------------------------`
59			`-- Revision Number : 5`
60			`-- Version : 0.5`
61			`-- Date : 9 April 2001`
62			`-- Modifier : Jamil Khatib (khatib@ieee.org)`
63			`-- Desccription : Rx Top components added`
64			`--`
65			`-------------------------------------------------------------------------------`
66			`-- $Log: not supported by cvs2svn $`
67			`-- Revision 1.11 2001/04/27 18:21:59 jamil`
68			`-- After Prelimenray simulation`
69			`--`
70			`-- Revision 1.10 2001/04/22 20:08:16 jamil`
71			`-- Top level simulation`
72			`--`
73			`-- Revision 1.7 2001/04/14 15:23:34 jamil`
74			`-- Rx Components added`
75			`--`
76			`-- Revision 1.6 2001/03/22 21:58:46 jamil`
77			`-- Top Tx Components added`
78			`--`
79			`-------------------------------------------------------------------------------`
80	2	khatib	`library ieee;`
81			`use ieee.std_logic_1164.all;`
82
83			`package hdlc_components_pkg is`
84
85	9	khatib	`component hdlc_ent`
86			`generic (`
87			`FCS_TYPE : integer;`
88			`ADD_WIDTH : integer);`
89			`port (`
90			`Txclk : in std_logic;`
91			`RxClk : in std_logic;`
92			`Tx : out std_logic;`
93			`Rx : in std_logic;`
94			`TxEN : in std_logic;`
95			`RxEn : in std_logic;`
96			`RST_I : in std_logic;`
97			`CLK_I : in std_logic;`
98			`ADR_I : in std_logic_vector(2 downto 0);`
99			`DAT_O : out std_logic_vector(31 downto 0);`
100			`DAT_I : in std_logic_vector(31 downto 0);`
101			`WE_I : in std_logic;`
102			`STB_I : in std_logic;`
103			`ACK_O : out std_logic;`
104			`CYC_I : in std_logic;`
105			`RTY_O : out std_logic;`
106			`TAG0_O : out std_logic;`
107			`TAG1_O : out std_logic);`
108			`end component;`
109
110
111			`constant ADD_WIDTH : integer := 7; -- Internal Buffers address width`
112			`component WB_IF_ent`
113			`generic (`
114			`ADD_WIDTH : integer);`
115			`port (`
116			`CLK_I : in std_logic;`
117			`RST_I : in std_logic;`
118			`ACK_O : out std_logic;`
119			`ADR_I : in std_logic_vector(2 downto 0);`
120			`CYC_I : in std_logic;`
121			`DAT_I : in std_logic_vector(31 downto 0);`
122			`DAT_O : out std_logic_vector(31 downto 0);`
123			`RTY_O : out std_logic;`
124			`STB_I : in std_logic;`
125			`WE_I : in std_logic;`
126			`TAG0_O : out std_logic;`
127			`TAG1_O : out std_logic;`
128			`TxEnable : out std_logic;`
129			`TxDone : in std_logic;`
130			`TxDataInBuff : out std_logic_vector(7 downto 0);`
131			`Txwr : out std_logic;`
132			`TxAborted : in std_logic;`
133			`TxAbort : out std_logic;`
134			`TxOverflow : in std_logic;`
135			`TxFCSen : out std_logic;`
136			`RxFrameSize : in std_logic_vector(ADD_WIDTH-1 downto 0);`
137			`RxRdy : in std_logic;`
138			`RxDataBuffOut : in std_logic_vector(7 downto 0);`
139			`RxOverflow : in std_logic;`
140			`RxFrameError : in std_logic;`
141			`RxFCSErr : in std_logic;`
142			`RxRd : out std_logic;`
143			`RxAbort : in std_logic);`
144			`end component;`
145
146			`component txSynch_ent`
147			`port (`
148			`rst_n : in std_logic;`
149			`clk_D1 : in std_logic;`
150			`clk_D2 : in std_logic;`
151			`rdy_D1 : in std_logic;`
152			`rdy_D2 : out std_logic;`
153			`ack : out std_logic;`
154			`TXD_D1 : out std_logic_vector(7 downto 0);`
155			`TXD_D2 : in std_logic_vector(7 downto 0);`
156			`ValidFrame_D1 : out std_logic;`
157			`ValidFrame_D2 : in std_logic;`
158			`AbortedTrans_D1 : in std_logic;`
159			`AbortedTrans_D2 : out std_logic;`
160			`AbortFrame_D1 : out std_logic;`
161			`AbortFrame_D2 : in std_logic;`
162			`WriteByte_D1 : out std_logic;`
163			`WriteByte_D2 : in std_logic);`
164			`end component;`
165
166			`component Txfcs_ent`
167			`generic (`
168			`FCS_TYPE : integer);`
169			`port (`
170			`TxClk : in std_logic;`
171			`rst_n : in std_logic;`
172			`FCSen : in std_logic;`
173			`ValidFrame : out std_logic;`
174			`WriteByte : out std_logic;`
175			`rdy : in std_logic;`
176			`ack : in std_logic;`
177			`TxData : out std_logic_vector(7 downto 0);`
178			`TxDataAvail : in std_logic;`
179			`RdBuff : out std_logic;`
180			`TxDataBuff : in std_logic_vector(7 downto 0));`
181			`end component;`
182
183			`component TxBuff_ent`
184			`generic (`
185			`ADD_WIDTH : integer);`
186			`port (`
187			`TxClk : in std_logic;`
188			`rst_n : in std_logic;`
189			`RdBuff : in std_logic;`
190			`Wr : in std_logic;`
191			`TxDataAvail : out std_logic;`
192			`TxEnable : in std_logic;`
193			`TxDone : out std_logic;`
194			`TxDataOutBuff : out std_logic_vector(7 downto 0);`
195			`TxDataInBuff : in std_logic_vector(7 downto 0);`
196			`Full : out std_logic);`
197			`end component;`
198
199	7	khatib	`component TxChannel_ent`
200			`port (`
201			`TxClk : in std_logic;`
202			`rst_n : in std_logic;`
203			`TXEN : in std_logic;`
204			`Tx : out std_logic;`
205			`ValidFrame : in std_logic;`
206			`AbortFrame : in std_logic;`
207			`AbortedTrans : out std_logic;`
208			`WriteByte : in std_logic;`
209			`rdy : out std_logic;`
210			`TxData : in std_logic_vector(7 downto 0));`
211			`end component;`
212
213			`component TxCont_ent`
214			`port (`
215			`TXclk : in std_logic;`
216			`rst_n : in std_logic;`
217			`TXEN : in std_logic;`
218			`enable : out std_logic;`
219			`BackendEnable : out std_logic;`
220			`abortedTrans : in std_logic;`
221			`inProgress : in std_logic;`
222			`ValidFrame : in std_logic;`
223			`Frame : out std_logic;`
224			`AbortFrame : in std_logic;`
225			`AbortTrans : out std_logic);`
226			`end component;`
227
228			`component flag_ins_ent`
229			`port (`
230			`TXclk : in std_logic;`
231			`rst_n : in std_logic;`
232			`TX : out std_logic;`
233			`TXEN : in std_logic;`
234			`TXD : in std_logic;`
235			`AbortFrame : in std_logic;`
236			`Frame : in std_logic);`
237			`end component;`
238
239			`component ZeroIns_ent`
240			`port (`
241			`TxClk : in std_logic;`
242			`rst_n : in std_logic;`
243			`enable : in std_logic;`
244			`BackendEnable : in std_logic;`
245			`abortedTrans : out std_logic;`
246			`inProgress : out std_logic;`
247			`ValidFrame : in std_logic;`
248			`Writebyte : in std_logic;`
249			`rdy : out std_logic;`
250			`TXD : out std_logic;`
251			`Data : in std_logic_vector(7 downto 0));`
252			`end component;`
253
254	2	khatib	`component rxcont_ent`
255			`port (`
256			`RxClk : in std_logic;`
257			`rst : in std_logic;`
258			`RxEn : in std_logic;`
259			`AbortedFrame : out std_logic;`
260			`Abort : in std_logic;`
261			`FlagDetect : in std_logic;`
262			`ValidFrame : out std_logic;`
263			`FrameError : out std_logic;`
264			`aval : in std_logic;`
265			`initzero : out std_logic;`
266			`enable : out std_logic);`
267			`end component;`
268
269
270			`component ZeroDetect_ent`
271			`port (`
272	9	khatib	`ValidFrame : in std_logic; --New`
273	2	khatib	`Readbyte : in std_logic;`
274			`aval : out std_logic;`
275			`enable : in std_logic;`
276			`StartOfFrame : in std_logic;`
277			`rdy : out std_logic;`
278			`rst : in std_logic;`
279			`RxClk : in std_logic;`
280			`RxD : in std_logic;`
281			`RxData : out std_logic_vector(7 downto 0));`
282			`end component;`
283
284			`component FlagDetect_ent`
285			`port (`
286			`Rxclk : in std_logic;`
287			`rst : in std_logic;`
288			`FlagDetect : out std_logic;`
289			`Abort : out std_logic;`
290	5	khatib	`RXEN : in std_logic;`
291			`RXEN_O : out std_logic;`
292	2	khatib	`RXD : out std_logic;`
293			`RX : in std_logic);`
294			`end component;`
295
296			`component RxChannel_ent`
297			`port (`
298			`Rxclk : in std_logic;`
299			`rst : in std_logic;`
300			`Rx : in std_logic;`
301			`RxData : out std_logic_vector(7 downto 0);`
302			`ValidFrame : out std_logic;`
303			`AbortSignal : out std_logic;`
304	5	khatib	`FrameError : out std_logic;`
305	2	khatib	`Readbyte : in std_logic;`
306			`rdy : out std_logic;`
307			`RxEn : in std_logic);`
308			`end component;`
309
310	9	khatib	`component RxSynch_ent`
311			`port (`
312			`rst_n : in std_logic;`
313			`clk_D1 : in std_logic;`
314			`clk_D2 : in std_logic;`
315			`rdy_D1 : in std_logic;`
316			`rdy_D2 : out std_logic;`
317			`RXD_D1 : in std_logic_vector(7 downto 0);`
318			`RXD_D2 : out std_logic_vector(7 downto 0);`
319			`ValidFrame_D1 : in std_logic;`
320			`ValidFrame_D2 : out std_logic;`
321			`AbortSignal_D1 : in std_logic;`
322			`AbortSignal_D2 : out std_logic;`
323			`FrameError_D1 : in std_logic;`
324			`FrameError_D2 : out std_logic;`
325			`ReadByte_D1 : out std_logic;`
326			`ReadByte_D2 : in std_logic);`
327			`end component;`
328
329			`component RxFCS_ent`
330			`generic (`
331			`FCS_TYPE : integer);`
332			`port (`
333			`clk : in std_logic;`
334			`rst_n : in std_logic;`
335			`RxD : in std_logic_vector(7 downto 0);`
336			`ValidFrame : in std_logic;`
337			`rdy : in std_logic;`
338			`Readbyte : out std_logic;`
339			`DataBuff : out std_logic_vector(7 downto 0);`
340			`WrBuff : out std_logic;`
341			`EOF : out std_logic;`
342			`FCSen : in std_logic;`
343			`FCSerr : out std_logic);`
344			`end component;`
345
346			`component RxBuff_ent`
347			`generic (`
348			`FCS_TYPE : integer;`
349			`ADD_WIDTH : integer);`
350			`port (`
351			`Clk : in std_logic;`
352			`rst_n : in std_logic;`
353			`DataBuff : in std_logic_vector(7 downto 0);`
354			`EOF : in std_logic;`
355			`WrBuff : in std_logic;`
356			`FrameSize : out std_logic_vector(ADD_WIDTH-1 downto 0);`
357			`RxRdy : out std_logic;`
358			`RxDataBuffOut : out std_logic_vector(7 downto 0);`
359			`Overflow : out std_logic;`
360			`Rd : in std_logic);`
361			`end component;`
362
363	2	khatib	`end hdlc_components_pkg;`

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