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khatib |
-------------------------------------------------------------------------------
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-- Title : Memory Package
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-- Project : Memory Cores
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-------------------------------------------------------------------------------
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-- File : mem_pkg.vhd
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-- Author : Jamil Khatib
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-- Organization: OpenIPCore Project
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-- Created : 2000/02/29
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-- Last update: 2001/03/20
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-- Platform :
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-- Simulators : Modelsim 5.2EE / Windows98, NC-Sim/Linux
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-- Synthesizers: Leonardo / Windows98
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-- Target : Flex10K
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-- Dependency : ieee.std_logic_1164
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-- utility.tools_pkg
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-------------------------------------------------------------------------------
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-- Description: Memory Package
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it under the terms of the Openip General Public
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-- License as it is going to be published by the OpenIPCore Organization and
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-- any coming versions of this license.
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-- You can check the draft license at
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-- http://www.openip.org/oc/license.html
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 1
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-- Version : 0.1
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-- Date : 29th Feb 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Created
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 2
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-- Version : 0.2
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-- Date : 29th Mar 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Memory components are added.
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--
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 3
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-- Version : 0.3
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-- Date : 12 Jan 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Memory components updated
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--
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 4
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-- Version : 0.31
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-- Date : 11 March 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : FIFO component added
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--
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 5
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-- Version : 0.5
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-- Date : 16 April 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : WISHBONE components added
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--
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-------------------------------------------------------------------------------
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2001/04/16 20:14:35 jamil
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-- WishBone components added
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--
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-- Revision 1.3 2001/03/20 19:39:32 jamil
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-- tools pkg bug fixed
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--
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-- Revision 1.2 2001/03/11 21:22:55 jamil
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-- FIFO component added
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library utility;
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use utility.tools_pkg.all;
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package mem_pkg is
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constant ADD_WIDTH : integer := 8; -- Address width
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constant WIDTH : integer := 4; -- Data width
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-------------------------------------------------------------------------------
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component dpmem_ent
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generic (
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USE_RESET : boolean;
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USE_CS : boolean;
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DEFAULT_OUT : std_logic;
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CLK_DOMAIN : integer;
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ADD_WIDTH : integer;
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WIDTH : integer);
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port (
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W_clk : in std_logic;
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R_clk : in std_logic;
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reset : in std_logic;
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W_add : in std_logic_vector(add_width -1 downto 0);
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R_add : in std_logic_vector(add_width -1 downto 0);
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Data_In : in std_logic_vector(WIDTH - 1 downto 0);
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Data_Out : out std_logic_vector(WIDTH -1 downto 0);
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WR : in std_logic;
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RE : in std_logic);
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end component;
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-------------------------------------------------------------------------------
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COMPONENT wb_dpmem
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GENERIC (
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ADD_WIDTH : INTEGER;
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WIDTH : INTEGER;
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CLK_DOMAIN : INTEGER);
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PORT (
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CLK_I_1 : IN STD_LOGIC;
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CLK_I_2 : IN STD_LOGIC;
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ADR_I_1 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
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ADR_I_2 : IN STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
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DAT_O : OUT STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
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DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
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WE_I_1 : IN STD_LOGIC;
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WE_I_2 : IN STD_LOGIC;
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ACK_O_1 : OUT STD_LOGIC;
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ACK_O_2 : OUT STD_LOGIC;
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STB_I_1 : IN STD_LOGIC;
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STB_I_2 : IN STD_LOGIC);
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END COMPONENT;
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-------------------------------------------------------------------------------
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component Spmem_ent
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generic (
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USE_RESET : boolean;
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USE_CS : boolean;
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DEFAULT_OUT : std_logic;
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OPTION : integer;
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ADD_WIDTH : integer;
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WIDTH : integer);
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port (
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cs : std_logic;
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clk : in std_logic;
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reset : in std_logic;
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add : in std_logic_vector(add_width -1 downto 0);
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Data_In : in std_logic_vector(WIDTH -1 downto 0);
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Data_Out : out std_logic_vector(WIDTH -1 downto 0);
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WR : in std_logic);
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end component;
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-------------------------------------------------------------------------------
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COMPONENT WB_spmem
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GENERIC (
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ADD_WIDTH : INTEGER;
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WIDTH : INTEGER;
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OPTION : INTEGER);
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PORT (
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DAT_O : OUT STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
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DAT_I : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
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CLK_I : IN STD_LOGIC;
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ADR_I : IN STD_LOGIC_VECTOR(ADD_WIDTH -1 DOWNTO 0);
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STB_I : IN STD_LOGIC;
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WE_I : IN STD_LOGIC;
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ACK_O : OUT STD_LOGIC);
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END COMPONENT;
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-------------------------------------------------------------------------------
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component FIFO_ent
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generic (
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ARCH : integer;
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USE_CS : boolean;
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DEFAULT_OUT : std_logic;
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CLK_DOMAIN : integer;
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MEM_CORE : integer;
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BLOCK_SIZE : integer;
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WIDTH : integer;
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DEPTH : integer);
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port (
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rst_n : in std_logic;
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Rclk : in std_logic;
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Wclk : in std_logic;
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cs : in std_logic;
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Din : in std_logic_vector(WIDTH-1 downto 0);
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Dout : out std_logic_vector(WIDTH-1 downto 0);
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Re : in std_logic;
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wr : in std_logic;
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UsedCount : out std_logic_vector(log2(DEPTH)-1 downto 0);
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RFull : out std_logic;
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RHalf_full : out std_logic;
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REmpty : out std_logic;
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WFull : out std_logic;
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WHalf_full : out std_logic;
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WEmpty : out std_logic);
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end component;
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end mem_pkg;
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-------------------------------------------------------------------------------
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