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-------------------------------------------------------------------------------
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-- Title : Rx Channel test bench
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-- Project : HDLC controller
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-------------------------------------------------------------------------------
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-- File : Rx_tb.vhd
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-- Author : Jamil Khatib (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Created : 2000/12/30
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-- Last update: 2001/01/12
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-- Platform :
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-- Simulators : Modelsim 5.3XE/Windows98
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-- Synthesizers:
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-- Target :
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-- Dependency : ieee.std_logic_1164
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--
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-------------------------------------------------------------------------------
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-- Description: receive Channel test bench
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 1
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-- Version : 0.1
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-- Date : 30 Dec 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Created
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-- ToOptimize : Add an input procedure to insert data pattern
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-- Bugs :
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-------------------------------------------------------------------------------
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khatib |
-- Revisions :
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-- Revision Number : 2
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-- Version : 0.2
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-- Date : 12 Jan 2001
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Rx Enable and delayed Read tests are added
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-- ToOptimize : Add an input procedure to insert data pattern
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-- Bugs :
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-------------------------------------------------------------------------------
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khatib |
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library ieee;
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use ieee.std_logic_1164.all;
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use work.hdlc_components_pkg.all;
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entity rx_tb_ent is
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end rx_tb_ent;
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architecture rx_tb_beh of rx_tb_ent is
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constant DataStreem : std_logic_vector(88 downto 0) := "11111111011111100100110011011111010001010011111101111000111101001101001011011011001111110";
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-- "1_11111110_11111100_10011001_10111110_10001010_01111110_11110001_11101001_10100101_10110110_01111110"
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signal Rxclk_i : std_logic := '0'; -- system clock
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signal rst_i : std_logic := '0'; -- system reset
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signal Rx_i : std_logic; -- internal Rx serial data
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signal RxData_i : std_logic_vector(7 downto 0); -- backend data bus
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signal ValidFrame_i : std_logic; -- backedn Valid frame signal
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signal AbortSignal_i : std_logic; -- backend abort signal
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signal Readbyte_i : std_logic; -- backend read byte
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signal rdy_i : std_logic; -- backend ready signal
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signal RxEn_i : std_logic; -- receive enable
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signal FrameError_i : std_logic; -- Frame Error
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begin -- rx_tb_beh
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-------------------------------------------------------------------------------
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Rxclk_i <= not Rxclk_i after 20 ns;
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rst_i <= '0',
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'1' after 30 ns;
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RxEn_i <= '1',
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'0' after 960 ns,
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'1' after 1280 ns;
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khatib |
-------------------------------------------------------------------------------
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-- purpose: Serial interface stimulus
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-- type : sequential
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-- inputs :
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-- outputs:
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serial_proc : process
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variable count : integer := 0; -- Counter
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begin -- process backend_proc
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wait until Rxclk_i = '0';
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rx_i <= DataStreem(count);
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if count = DataStreem'length-1 then
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count := 0;
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else
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count := count +1;
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end if;
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end process serial_proc;
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-------------------------------------------------------------------------------
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-- purpose: Backend stimulus
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-- type : combinational
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-- inputs :
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-- outputs:
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backend_proc : process(rdy_i)
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variable counter : integer := 0; -- Counter
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begin -- process backend_proc
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if rdy_i = '1' then
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-- Counter is used to generate Readbyte signal at different delays
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if not((counter > 20) and (counter < 40)) then
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Readbyte_i <= '1' after 60 ns;
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elsif(counter mod 2 = 0) then
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-- data bits will be lost in this case
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Readbyte_i <= '1' after 350 ns;
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else
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Readbyte_i <= '1' after 60 ns;
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end if;
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counter := counter+1;
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else
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Readbyte_i <= '0';
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end if;
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end process backend_proc;
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-------------------------------------------------------------------------------
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uut : RxChannel_ent
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port map (
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Rxclk => Rxclk_i,
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rst => rst_i,
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Rx => Rx_i,
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RxData => RxData_i,
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ValidFrame => ValidFrame_i,
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FrameError => FrameError_i,
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AbortSignal => AbortSignal_i,
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Readbyte => Readbyte_i,
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rdy => rdy_i,
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RxEn => RxEn_i);
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end rx_tb_beh;
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