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[/] [hdlc/] [trunk/] [CODE/] [SPMEM.VHD] - Blame information for rev 17

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1 9 khatib 
-------------------------------------------------------------------------------
2 
-- Title      :  Single port RAM
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-- Project    :  Memory Cores
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-------------------------------------------------------------------------------
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-- File        : spmem.vhd
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-- Author      : Jamil Khatib  (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Created     : 1999/5/14
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-- Last update : 2000/12/19
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-- Platform    :
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-- Simulators  : Modelsim 5.3XE/Windows98
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-- Synthesizers: Leonardo/WindowsNT
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-- Target      :
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-- Dependency  : ieee.std_logic_1164,ieee.std_logic_unsigned
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-------------------------------------------------------------------------------
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-- Description:  Single Port memory
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1
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-- Version         :   0.1
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-- Date            :   12 May 1999
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Created
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   2
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-- Version         :   0.2
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-- Date            :   19 Dec 2000
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   General review
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--                     Two versions are now available with reset and without
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--                     Default output can can be defined
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   3
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-- Version         :   0.3
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-- Date            :   5 Jan 2001
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Registered Read Address feature is added to make use of
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--                     Altera's FPGAs memory bits
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--                     This feature was added from Richard Herveille's
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--                     contribution and his memory core
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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59 
 
60 
 
61 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-------------------------------------------------------------------------------
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-- Single port Memory core with reset
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-- To make use of on FPGA memory bits do not use the RESET option
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-- For Altera's FPGA you have to use also OPTION := 1
68 
 
69 
entity Spmem_ent is
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  generic ( USE_RESET   : boolean   := false;  -- use system reset
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            USE_CS      : boolean   := false;  -- use chip select signal
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            DEFAULT_OUT : std_logic := '1';  -- Default output
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            OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
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                                        -- for Altera's FPGAs
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                                        -- 0: non registered read address
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            ADD_WIDTH   : integer   := 3;
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            WIDTH       : integer   := 8);
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  port (
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    cs       :     std_logic;           -- chip select
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    clk      : in  std_logic;           -- write clock
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    reset    : in  std_logic;           -- System Reset
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    add      : in  std_logic_vector(add_width -1 downto 0);  --  Address
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    Data_In  : in  std_logic_vector(WIDTH -1 downto 0);  -- input data
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    Data_Out : out std_logic_vector(WIDTH -1 downto 0);  -- Output Data
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    WR       : in  std_logic);          -- Read Write Enable
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end Spmem_ent;
88 
 
89 
 
90 
 
91 
-------------------------------------------------------------------------------
92 
-- This Architecture was tested on the ModelSim 5.2EE
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-- The test vectors for model sim is included in vectors.do file
94 
 
95 
 
96 
architecture spmem_beh of Spmem_ent is
97 
 
98 
 
99 
 
100 
  type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
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                                                      -- Memory Type
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  signal data : data_array(0 to (2** add_width-1) );  -- Local data
103 
 
104 
 
105 
        -- FLEX/APEX devices require address to be registered with inclock for read operations
106 
  -- This signal is used only when OPTION = 1
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        signal regA : std_logic_vector( (add_width -1) downto 0);
108 
 
109 
  procedure init_mem(signal memory_cell : inout data_array ) is
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  begin
111 
 
112 
    for i in 0 to (2** add_width-1) loop
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      memory_cell(i) <= (others => '0');
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    end loop;
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116 
  end init_mem;
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begin  -- spmem_beh
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-------------------------------------------------------------------------------
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-- Non Registered Read Address
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-------------------------------------------------------------------------------
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  NON_REG         : if OPTION = 0 generate
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-------------------------------------------------------------------------------
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-- Clocked Process with Reset
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-------------------------------------------------------------------------------
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    Reset_ENABLED : if USE_RESET = true generate
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-------------------------------------------------------------------------------
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      CS_ENABLED  : if USE_CS = true generate
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        process (clk, reset)
130 
 
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        begin  -- PROCESS
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          -- activities triggered by asynchronous reset (active low)
133 
 
134 
          if reset = '0' then
135 
            data_out <= (others => DEFAULT_OUT);
136 
            init_mem ( data);
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138 
            -- activities triggered by rising edge of clock
139 
          elsif clk'event and clk = '1' then
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            if CS = '1' then
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              if WR = '0' then
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                data(conv_integer(add)) <= data_in;
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                data_out                <= (others => DEFAULT_OUT);
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              else
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                data_out                <= data(conv_integer(add));
146 
              end if;
147 
            else
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              data_out                  <= (others => DEFAULT_OUT);
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            end if;
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151 
          end if;
152 
 
153 
        end process;
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      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
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        process (clk, reset)
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160 
 
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        begin  -- PROCESS
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          -- activities triggered by asynchronous reset (active low)
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          if reset = '0' then
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            data_out <= (others => DEFAULT_OUT);
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            init_mem ( data);
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            -- activities triggered by rising edge of clock
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          elsif clk'event and clk = '1' then
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            if WR = '0' then
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              data(conv_integer(add)) <= data_in;
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              data_out                <= (others => DEFAULT_OUT);
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            else
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              data_out                <= data(conv_integer(add));
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            end if;
176 
 
177 
          end if;
178 
 
179 
        end process;
180 
      end generate CS_DISABLED;
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-------------------------------------------------------------------------------
183 
-------------------------------------------------------------------------------
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    end generate Reset_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Clocked Process without Reset
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-------------------------------------------------------------------------------
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    Reset_DISABLED : if USE_RESET = false generate
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_ENABLED   : if USE_CS = true generate
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        process (clk)
195 
        begin  -- PROCESS
196 
 
197 
          -- activities triggered by rising edge of clock
198 
          if clk'event and clk = '1' then
199 
            if cs = '1' then
200 
              if WR = '0' then
201 
                data(conv_integer(add)) <= data_in;
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                data_out                <= (others => DEFAULT_OUT);
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              else
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                data_out                <= data(conv_integer(add));
205 
              end if;
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            else
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              data_out                  <= (others => DEFAULT_OUT);
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            end if;
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211 
          end if;
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213 
        end process;
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      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
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        process (clk)
219 
        begin  -- PROCESS
220 
 
221 
          -- activities triggered by rising edge of clock
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          if clk'event and clk = '1' then
223 
            if WR = '0' then
224 
              data(conv_integer(add)) <= data_in;
225 
              data_out                <= (others => DEFAULT_OUT);
226 
            else
227 
              data_out                <= data(conv_integer(add));
228 
            end if;
229 
 
230 
          end if;
231 
 
232 
        end process;
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      end generate CS_DISABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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    end generate Reset_DISABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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  end generate NON_REG;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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REG: if OPTION = 1 generate
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-------------------------------------------------------------------------------
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-- Clocked Process with Reset
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-------------------------------------------------------------------------------
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    Reset_ENABLED : if USE_RESET = true generate
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-------------------------------------------------------------------------------
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      CS_ENABLED  : if USE_CS = true generate
252 
        process (clk, reset)
253 
 
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        begin  -- PROCESS
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          -- activities triggered by asynchronous reset (active low)
256 
 
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          if reset = '0' then
258 
            data_out <= (others => DEFAULT_OUT);
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            init_mem ( data);
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261 
            -- activities triggered by rising edge of clock
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          elsif clk'event and clk = '1' then
263 
 
264 
            regA <= add;
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266 
            if CS = '1' then
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              if WR = '0' then
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                data(conv_integer(add)) <= data_in;
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                data_out                <= (others => DEFAULT_OUT);
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              else
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                data_out                <= data(conv_integer(regA));
272 
              end if;
273 
            else
274 
              data_out                  <= (others => DEFAULT_OUT);
275 
            end if;
276 
 
277 
          end if;
278 
 
279 
        end process;
280 
      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
284 
        process (clk, reset)
285 
 
286 
 
287 
        begin  -- PROCESS
288 
          -- activities triggered by asynchronous reset (active low)
289 
 
290 
          if reset = '0' then
291 
            data_out <= (others => DEFAULT_OUT);
292 
            init_mem ( data);
293 
 
294 
            -- activities triggered by rising edge of clock
295 
          elsif clk'event and clk = '1' then
296 
            regA <= add;
297 
 
298 
            if WR = '0' then
299 
              data(conv_integer(add)) <= data_in;
300 
              data_out                <= (others => DEFAULT_OUT);
301 
            else
302 
              data_out                <= data(conv_integer(regA));
303 
            end if;
304 
 
305 
          end if;
306 
 
307 
        end process;
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      end generate CS_DISABLED;
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310 
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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    end generate Reset_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Clocked Process without Reset
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-------------------------------------------------------------------------------
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    Reset_DISABLED : if USE_RESET = false generate
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_ENABLED   : if USE_CS = true generate
322 
        process (clk)
323 
        begin  -- PROCESS
324 
 
325 
          -- activities triggered by rising edge of clock
326 
          if clk'event and clk = '1' then
327 
 
328 
            regA <= add;
329 
 
330 
            if cs = '1' then
331 
              if WR = '0' then
332 
                data(conv_integer(add)) <= data_in;
333 
                data_out                <= (others => DEFAULT_OUT);
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              else
335 
                data_out                <= data(conv_integer(regA));
336 
              end if;
337 
            else
338 
              data_out                  <= (others => DEFAULT_OUT);
339 
            end if;
340 
 
341 
 
342 
          end if;
343 
 
344 
        end process;
345 
      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
349 
        process (clk)
350 
        begin  -- PROCESS
351 
 
352 
          -- activities triggered by rising edge of clock
353 
          if clk'event and clk = '1' then
354 
 
355 
            regA <= add;
356 
 
357 
            if WR = '0' then
358 
              data(conv_integer(add)) <= data_in;
359 
              data_out                <= (others => DEFAULT_OUT);
360 
            else
361 
              data_out                <= data(conv_integer(regA));
362 
            end if;
363 
 
364 
          end if;
365 
 
366 
        end process;
367 
      end generate CS_DISABLED;
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-------------------------------------------------------------------------------
369 
-------------------------------------------------------------------------------
370 
    end generate Reset_DISABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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375 
end generate REG;
376 
 
377 
end spmem_beh;
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-------------------------------------------------------------------------------

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