OpenCores
URL https://opencores.org/ocsvn/hdlc/hdlc/trunk

Subversion Repositories hdlc

[/] [hdlc/] [trunk/] [CODE/] [TOP/] [core/] [RxSync.vhd] - Blame information for rev 17

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 khatib
-------------------------------------------------------------------------------
2
-- Title      : Rx Synchronizer
3
-- Project    : HDLC controller
4
-------------------------------------------------------------------------------
5
-- File       : RxSync.vhd
6
-- Author     : Jamil Khatib  <khatib@ieee.org>
7
-- Organization: OpenCores Project
8
-- Created    : 2001/04/04
9
-- Last update: 2001/04/04
10
-- Platform   : 
11
-- Simulators  : Modelsim/Win98 , NC-sim/Linux
12
-- Synthesizers: 
13
-- Target      : 
14
-- Dependency  : ieee.std_logic
15
-------------------------------------------------------------------------------
16
-- Description: Rx Synchronizer
17
-------------------------------------------------------------------------------
18
-- Copyright (c) 2001  Jamil Khatib
19
-- 
20
-- This VHDL design file is an open design; you can redistribute it and/or
21
-- modify it and/or implement it after contacting the author
22
-- You can check the draft license at
23
-- http://www.opencores.org/OIPC/license.shtml
24
-------------------------------------------------------------------------------
25
-- Revisions  :
26
-- Revision Number :   1
27
-- Version         :   0.1
28
-- Date            :  2001/04/04
29
-- Modifier        :  Jamil Khatib  <khatib@ieee.org>
30
-- Desccription    :  Created
31
-- ToOptimize      :
32
-- Known Bugs      :
33
-------------------------------------------------------------------------------
34
-- $Log: not supported by cvs2svn $
35
-- Revision 1.1  2001/04/14 15:02:25  jamil
36
-- Initial Release
37
--
38
-------------------------------------------------------------------------------
39
 
40
LIBRARY ieee;
41
USE ieee.std_logic_1164.ALL;
42
 
43
ENTITY RxSynch_ent IS
44
  -- D1 Domain 1 = Serial line
45
  -- D2 Domain 2 = System interface
46
  PORT (
47
    rst_n          : IN  STD_LOGIC;     -- System reset
48
    clk_D1         : IN  STD_LOGIC;     -- Domain 1 clock
49
    clk_D2         : IN  STD_LOGIC;     -- Domain 2 clock
50
    rdy_D1         : IN  STD_LOGIC;     -- Domain 1 ready
51
    rdy_D2         : OUT STD_LOGIC;     -- Domain 2 ready
52
    RXD_D1         : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Domain 1 Rx Data bus
53
    RXD_D2         : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Domain 2 Rx Data Bus
54
    ValidFrame_D1  : IN  STD_LOGIC;     -- Domain 1 Valid Frame
55
    ValidFrame_D2  : OUT STD_LOGIC;     -- Domain 2 Valid Frame
56
    AbortSignal_D1 : IN  STD_LOGIC;     -- Domain 1 Abort signal
57
    AbortSignal_D2 : OUT STD_LOGIC;     -- Domain 2 Abort signal
58
    FrameError_D1  : IN  STD_LOGIC;     -- Domain 1 Frame Error
59
    FrameError_D2  : OUT STD_LOGIC;     -- Domain 2 Frame Error
60
    ReadByte_D1    : OUT STD_LOGIC;     -- Domain 1 Read Byte
61
    ReadByte_D2    : IN  STD_LOGIC      -- Domain 2 Read Byte
62
 
63
    );
64
 
65
END RxSynch_ent;
66
-------------------------------------------------------------------------------
67
 
68
ARCHITECTURE RxSynch_rtl OF RxSynch_ent IS
69
 
70
BEGIN  -- ARCHITECTURE RxSynch_rtl
71
 
72
-- Data bus does not need synchronization  
73
  RXD_D2 <= RXD_D1;
74
 
75
  -- purpose: rdy signal
76
  -- type   : sequential
77
  -- inputs : clk_D2, rst_n
78
  -- outputs: 
79
  Rdy_signal     : PROCESS (clk_D2, rst_n)
80
    VARIABLE FF1 : STD_LOGIC;
81
  BEGIN  -- PROCESS Rdy_signal
82
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
83
      FF1    := '0';
84
      rdy_D2 <= '0';
85
    ELSIF clk_D2'event AND clk_D2 = '1' THEN  -- rising clock edge
86
      rdy_D2 <= FF1;
87
      FF1    := rdy_D1;
88
    END IF;
89
 
90
  END PROCESS Rdy_signal;
91
 
92
  -- purpose: Read bytes signal
93
  -- type   : sequential
94
  -- inputs : clk_D1, rst_n
95
  -- outputs: 
96
  Read_signal    : PROCESS (clk_D1, rst_n)
97
    VARIABLE FF1 : STD_LOGIC;
98
  BEGIN  -- PROCESS Read_signal
99
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
100
      FF1         := '0';
101
      ReadByte_D1 <= '0';
102
    ELSIF clk_D1'event AND clk_D1 = '1' THEN  -- rising clock edge
103
      ReadByte_D1 <= FF1;
104
      FF1         := ReadByte_D2;
105
    END IF;
106
  END PROCESS Read_signal;
107
 
108
 
109
  -- purpose: Valid Frame signal
110
  -- type   : sequential
111
  -- inputs : clk_D2, rst_n
112
  -- outputs: 
113
  ValidFrame_signal : PROCESS (clk_D2, rst_n)
114
    VARIABLE FF1    : STD_LOGIC;
115
  BEGIN  -- PROCESS ValidFrame_signal
116
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
117
      FF1           := '0';
118
      ValidFrame_D2 <= '0';
119
    ELSIF clk_D2'event AND clk_D2 = '1' THEN  -- rising clock edge
120
      ValidFrame_D2 <= FF1;
121
      FF1           := ValidFrame_D1;
122
    END IF;
123
  END PROCESS ValidFrame_signal;
124
 
125
  -- purpose: Abort  signal
126
  -- type   : sequential
127
  -- inputs : clk_D2, rst_n
128
  -- outputs: 
129
  Abort_signal   : PROCESS (clk_D2, rst_n)
130
    VARIABLE FF1 : STD_LOGIC;
131
  BEGIN  -- PROCESS AbortedTrans_signal
132
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
133
      FF1            := '0';
134
      AbortSignal_D2 <= '0';
135
    ELSIF clk_D2'event AND clk_D2 = '1' THEN  -- rising clock edge
136
      AbortSignal_D2 <= FF1;
137
      FF1            := AbortSignal_D1;
138
    END IF;
139
  END PROCESS Abort_signal;
140
 
141
 
142
  -- purpose: Error signal
143
  -- type   : sequential
144
  -- inputs : clk_D2, rst_n
145
  -- outputs: 
146
  Error_signal   : PROCESS (clk_D2, rst_n)
147
    VARIABLE FF1 : STD_LOGIC;
148
  BEGIN  -- PROCESS FrameError_signal
149
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)
150
      FF1           := '0';
151
      FrameError_D2 <= '0';
152
    ELSIF clk_D2'event AND clk_D2 = '1' THEN  -- rising clock edge
153
      FrameError_D2 <= FF1;
154
      FF1           := FrameError_D1;
155
    END IF;
156
  END PROCESS Error_signal;
157
 
158
END RxSynch_rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.