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[/] [hdlc/] [trunk/] [CODE/] [TOP/] [core/] [WB_IF.vhd] - Blame information for rev 17

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-------------------------------------------------------------------------------
-- Title      :  WISHBONE bus interface
-- Project    :  HDLC controller
-------------------------------------------------------------------------------
-- File        : WB_IF.vhd
-- Author      : Jamil Khatib  (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created     :2001/04/11
-- Last update:2001/04/18
-- Platform :
-- Simulators  : Modelsim 5.3XE/Windows98,NC-SIM/Linux
-- Synthesizers: 
-- Target      : 
-- Dependency  : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description:  Wishbone bus interface
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :  11 April 2001
-- Modifier        :   Jamil Khatib (khatib@ieee.org)
-- Desccription    :   Created
-- ToOptimize      :
-- Bugs            :   
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.3  2001/04/27 18:21:59  jamil
-- After Prelimenray simulation
--
-- Revision 1.2  2001/04/22 20:08:16  jamil
-- Top level simulation
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY WB_IF_ent IS
  GENERIC (
    ADD_WIDTH : integer := 7);          -- Address width
 
  PORT (
    -- WB Bus ports
    CLK_I  : IN  std_logic;                      -- System Clock
    RST_I  : IN  std_logic;                      -- System Reset
    ACK_O  : OUT std_logic;                      -- acknowledge
    ADR_I  : IN  std_logic_vector(2 DOWNTO 0);   -- address
    CYC_I  : IN  std_logic;                      -- Bus cycle
    DAT_I  : IN  std_logic_vector(31 DOWNTO 0);  -- Input data
    DAT_O  : OUT std_logic_vector(31 DOWNTO 0);  -- Output data
    RTY_O  : OUT std_logic;                      -- retry
    STB_I  : IN  std_logic;                      -- strobe
    WE_I   : IN  std_logic;                      -- Write
    TAG0_O : OUT std_logic;                      -- TAG0 (TxDone)
    TAG1_O : OUT std_logic;                      -- TAG1_O (RxRdy)
 
-- Internal ports
    -- Tx
    TxEnable     : OUT std_logic;       -- TxEnable (Write Frame completed)
    TxDone       : IN  std_logic;       -- Transmission Done (Read Frame completed)
    TxDataInBuff : OUT std_logic_vector(7 DOWNTO 0);  -- Input Data
    Txwr         : OUT std_logic;       -- Tx Write Buffer
    TxAborted    : IN  std_logic;       -- Aborted Frame
    TxAbort      : OUT std_logic;       -- Abort Transmission
    TxOverflow   : IN  std_logic;       -- Tx Buffer Overflow
    TxFCSen      : OUT std_logic;       -- FCS enable;
 
    -- Rx
    RxFrameSize   : IN  std_logic_vector(ADD_WIDTH-1 DOWNTO 0);  -- Frame Length
    RxRdy         : IN  std_logic;      -- Rx Ready
    RxDataBuffOut : IN  std_logic_vector(7 DOWNTO 0);  -- Output Rx Buffer
    RxOverflow    : IN  std_logic;      -- Rx Buffer Overflow
    RxFrameError  : IN  std_logic;      -- Frame Error
    RxFCSErr      : IN  std_logic;      -- Rx FCS Error
    RxRd          : OUT std_logic;      -- Rx Read data
    RxAbort       : IN  std_logic       -- Received Abort signal
 
    );
 
END WB_IF_ent;
 
ARCHITECTURE WB_IF_rtl OF WB_IF_ent IS
  SIGNAL ack_0 : std_logic;             -- ack Reg 0
  SIGNAL ack_1 : std_logic;             -- ack Reg 1
  SIGNAL ack_2 : std_logic;             -- ack Reg 2
  SIGNAL ack_3 : std_logic;             -- ack Reg 3
  SIGNAL ack_4 : std_logic;             -- ack Reg 4
 
  SIGNAL DATO_0 : std_logic_vector(31 DOWNTO 0);  -- data out 0
  SIGNAL DATO_1 : std_logic_vector(31 DOWNTO 0);  -- data out 1
  SIGNAL DATO_2 : std_logic_vector(31 DOWNTO 0);  -- data out 2
  SIGNAL DATO_3 : std_logic_vector(31 DOWNTO 0);  -- data out 3
  SIGNAL DATO_4 : std_logic_vector(31 DOWNTO 0);  -- data out 4
 
  SIGNAL en_0 : std_logic;              -- Enable reg 0
  SIGNAL en_1 : std_logic;              -- Enable reg 1
  SIGNAL en_2 : std_logic;              -- Enable reg 2
  SIGNAL en_3 : std_logic;              -- Enable reg 3
  SIGNAL en_4 : std_logic;              -- Enable reg 4
 
  SIGNAL counter   : integer RANGE 0 TO 7;  -- System counter
  SIGNAL rst_count : std_logic;             -- Reset counter
 
BEGIN  -- WB_IF_rtl
 
-- purpose: WB fsm
-- type   : sequential
-- inputs : CLK_I, RST_I
-- outputs: 
  WB_fsm : PROCESS (CLK_I, RST_I)
 
  BEGIN  -- PROCESS WB_fsm
    IF (CLK_I'event AND CLK_I = '1') THEN
      RTY_O <= '0';
 
      IF (RST_I = '1') THEN             -- synchronous reset
 
        ACK_O  <= '0';
        DAT_O  <= (OTHERS => '0');
        RTY_O  <= '0';
        TAG0_O <= '0';
        TAG1_O <= '0';
 
        en_0      <= '0';
        en_1      <= '0';
        en_2      <= '0';
        en_3      <= '0';
        en_4      <= '0';
        rst_count <= '1';
 
      ELSE
        TAG0_O <= TxDone;
        TAG1_O <= RxRdy;
 
        IF (CYC_I = '1' AND STB_I = '1') THEN
 
          CASE ADR_I IS
            WHEN "000" =>               -- Tx_SC
              ACK_O <= ack_0;
              DAT_O <= DATO_0;
 
              en_0      <= '1';
              en_1      <= '0';
              en_2      <= '0';
              en_3      <= '0';
              en_4      <= '0';
              rst_count <= '1';
 
            WHEN "001" =>               -- Tx_Buff
              ACK_O <= ack_1;
              DAT_O <= DATO_1;
 
              en_0 <= '0';
              en_1 <= '1' and not ack_1;
              en_2 <= '0';
              en_3 <= '0';
              en_4 <= '0';
 
              IF counter = 4 THEN
                rst_count <= '1';
                else
                  rst_count <= '0';
              END IF;
 
            WHEN "010" =>               -- Rx_SC
              ACK_O <= ack_2;
              DAT_O <= DATO_2;
 
              en_0 <= '0';
              en_1 <= '0';
              en_2 <= '1';
              en_3 <= '0';
              en_4 <= '0';
 
            WHEN "011" =>               -- Rx_Buff
              ACK_O <= ack_3;
              DAT_O <= DATO_3;
 
              en_0 <= '0';
              en_1 <= '0';
              en_2 <= '0';
              en_3 <= '1' and not ack_3;
              en_4 <= '0';
 
              IF counter = 7 THEN
                rst_count <= '1';
                else
                  rst_count <= '0';
              END IF;
 
            WHEN "100" =>               -- Rx_len
              ACK_O <= ack_4;
              DAT_O <= DATO_4;
 
              en_0 <= '0';
              en_1 <= '0';
              en_2 <= '0';
              en_3 <= '0';
              en_4 <= '1';
 
            WHEN OTHERS        =>
              DAT_O <= (OTHERS => '0');
              ACK_O <= '1';
 
              en_0 <= '0';
              en_1 <= '0';
              en_2 <= '0';
              en_3 <= '0';
              en_4 <= '0';
 
          END CASE;
 
        ELSE
 
          DAT_O <= (OTHERS => '0');
          ACK_O <= '0';
 
          en_0 <= '0';
          en_1 <= '0';
          en_2 <= '0';
          en_3 <= '0';
          en_4 <= '0';
 
        END IF;  -- cycle
 
      END IF;  --clock
 
    END IF;  -- reset
 
  END PROCESS WB_fsm;
 
-------------------------------------------------------------------------------
  -- purpose: Register0
  -- type   : sequential
  -- inputs : CLK_I, RST_I
  -- outputs: 
  reg0 : PROCESS (CLK_I, RST_I)
 
  BEGIN  -- PROCESS reg0
    IF (CLK_I'event AND CLK_I = '1') THEN
 
      IF (RST_I = '1') THEN
        ack_0    <= '0';
        DATO_0   <= (OTHERS => '0');
        TxEnable <= '0';
        TxAbort  <= '0';
        TxFCSen  <= '1';
 
      ELSE
        DATO_0 <= "000000000000000000000000"&
                  "00" & '0'& TxOverflow & TxAborted & "00" & TxDone;
        ack_0  <= en_0;
 
        IF (en_0 = '1' AND WE_I = '1') THEN
 
          TxEnable <= DAT_I(1);
          TxAbort  <= DAT_I(2);
          TxFCSen  <= DAT_I(5);
 
        END IF;  -- Write and en_0
 
 
      END IF;  -- rst
    END IF;  -- clk
 
  END PROCESS reg0;
-------------------------------------------------------------------------------
  -- purpose: Register1
  -- type   : sequential
  -- inputs : CLK_I, RST_I
  -- outputs: 
  reg1 : PROCESS (CLK_I, RST_I)
 
--    VARIABLE counter : integer RANGE 0 TO 3;  -- Internal counter
 
  BEGIN  -- PROCESS reg1
    IF (CLK_I'event AND CLK_I = '1') THEN
 
      IF (RST_I = '1') THEN
        ack_1   <= '0';
        DATO_1  <= (OTHERS => '0');
--        counter := 0;
 
      ELSE                              -- reset
        DATO_1 <= (OTHERS => '0');
 
        IF (WE_I = '1' AND en_1 = '1') THEN
 
--          Txwr             <= '1';
          CASE counter IS
            WHEN 0      =>
          Txwr             <= '1';
              TxDataInBuff <= DAT_I(7 DOWNTO 0);
              ack_1        <= '0';
--              counter      := counter + 1;
            WHEN 1      =>
          Txwr             <= '1';
              TxDataInBuff <= DAT_I(15 DOWNTO 8);
              ack_1        <= '0';
--              counter      := counter + 1;
            WHEN 2      =>
          Txwr             <= '1';
              TxDataInBuff <= DAT_I(23 DOWNTO 16);
              ack_1        <= '0';
--              counter      := counter + 1;
            WHEN 3      =>
          Txwr             <= '1';
              TxDataInBuff <= DAT_I(31 DOWNTO 24);
              ack_1        <= '1';
--              counter      := 0;
            WHEN OTHERS =>
          Txwr             <= '0';
                TxDataInBuff <= (others=> '0');
              ack_1        <= '0';
          END CASE;
 
        ELSE                            -- WE_I
 
          TxDataInBuff <= (OTHERS => '0');
--          counter      := 0;
          Txwr         <= '0';
          ack_1        <= '0';
        END IF;  -- WE_I and en_1
 
 
      END IF;  -- rst
    END IF;  -- clk
 
  END PROCESS reg1;
 
-------------------------------------------------------------------------------
  -- purpose: Register2
  -- type   : sequential
  -- inputs : CLK_I, RST_I
  -- outputs: 
  reg2 : PROCESS (CLK_I, RST_I)
 
  BEGIN  -- PROCESS reg3
    IF (CLK_I'event AND CLK_I = '1') THEN
 
      IF (RST_I = '1') THEN
        ack_2  <= '0';
        DATO_2 <= (OTHERS => '0');
 
      ELSE
        DATO_2 <= "000000000000000000000000"&
                  "000"& RxOverflow & RxAbort & RxFrameError & RxFCSErr & RxRdy;
        ack_2  <= en_2;
 
      END IF;  -- rst
    END IF;  -- clk
 
  END PROCESS reg2;
-------------------------------------------------------------------------------
  -- purpose: Register3
  -- type   : sequential
  -- inputs : CLK_I, RST_I
  -- outputs: 
  reg3 : PROCESS (CLK_I, RST_I)
 
--    VARIABLE count : integer RANGE 0 TO 5;  -- Internal counter
 
  BEGIN  -- PROCESS reg1
    IF (CLK_I'event AND CLK_I = '1') THEN
 
      IF (RST_I = '1') THEN
        ack_3   <= '0';
        DATO_3  <= (OTHERS => '0');
  --      count := 0;
 
      ELSE
 
        IF (en_3 = '1' AND WE_I = '0') THEN
 
--          if (WE_I = '0') then
 
          CASE counter IS
            WHEN 0               =>
              RxRd    <= '1';
              DATO_3  <= (OTHERS => '0');
              ack_3   <= '0';
--              count := count + 1;
 
            WHEN 1               =>
              RxRd    <= '1';
--                DATO_3  <= "000000000000000000000000" & RxDataBuffOut;
              DATO_3  <= RxDataBuffOut & DATO_3(31 downto 8);
--              DATO_3  <= (OTHERS => '0');
              ack_3   <= '0';
--              count := count + 1;
 
            WHEN 2 =>
              RxRd    <= '1';
              DATO_3  <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
              ack_3   <= '0';
--              count := count + 1;
 
            WHEN 3 =>
              RxRd <= '0';
 
              DATO_3  <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
              ack_3   <= '0';
--              count := count + 1;
            WHEN 4 =>
              RxRd    <= '0';
 
              DATO_3  <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
              ack_3   <= '0';
--              count := count +1;
            WHEN 5 =>
              RxRd    <= '0';
 
              DATO_3  <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
              ack_3   <= '1';
----              count := 0;
 
            WHEN OTHERS =>
              RxRd    <= '0';
 
              DATO_3  <= (others=>'0');
              ack_3   <= '0';
          END CASE;
 
--          else
--            DATO_3  <= (others => '0');
--            counter := 0;
--            RxRd    <= '0';
--            ack_3   <= '0';
 
--          end if;                     -- Write
 
        ELSE
          DATO_3  <= (OTHERS => '0');
--          count := 0;
          RxRd    <= '0';
          ack_3   <= '0';
 
        END IF;  -- en
 
      END IF;  -- rst
    END IF;  -- clk
 
  END PROCESS reg3;
 
  -----------------------------------------------------------------------------
  -- purpose: Register4
  -- type   : sequential
  -- inputs : CLK_I, RST_I
  -- outputs: 
  reg4 : PROCESS (CLK_I, RST_I)
 
  BEGIN  -- PROCESS reg4
    IF (CLK_I'event AND CLK_I = '1') THEN
 
      IF (RST_I = '1') THEN
        ack_4  <= '0';
        DATO_4 <= (OTHERS => '0');
 
      ELSE
        DATO_4 <= "000000000000000000000000"&
                  '0' & RxFrameSize;
        ack_4  <= en_4;
 
      END IF;  -- rst
    END IF;  -- clk
 
  END PROCESS reg4;
  -----------------------------------------------------------------------------
 
-- purpose: system counter
-- type   : sequential
-- inputs : CLK_I
-- outputs: 
  sys_counter : PROCESS (CLK_I)
  BEGIN  -- process sys_counter
 
    IF CLK_I'event AND CLK_I = '1' THEN  -- rising clock edge
 
      IF rst_count = '1' THEN
 
        counter <= 0;
 
      ELSIF en_1 = '1' OR en_3 = '1' THEN
 
        counter <= counter +1;
 
        ELSE
        counter <= 0;
      END IF;
    END IF;
  END PROCESS sys_counter;
  -----------------------------------------------------------------------------
 
END WB_IF_rtl;

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[/] [hdlc/] [trunk/] [CODE/] [TOP/] [core/] [WB_IF.vhd] - Blame information for rev 17

Line No.	Rev	Author	Line
1	10	khatib	`-------------------------------------------------------------------------------`
2			`-- Title : WISHBONE bus interface`
3			`-- Project : HDLC controller`
4			`-------------------------------------------------------------------------------`
5			`-- File : WB_IF.vhd`
6			`-- Author : Jamil Khatib (khatib@ieee.org)`
7			`-- Organization: OpenIPCore Project`
8			`-- Created :2001/04/11`
9			`-- Last update:2001/04/18`
10			`-- Platform :`
11			`-- Simulators : Modelsim 5.3XE/Windows98,NC-SIM/Linux`
12			`-- Synthesizers:`
13			`-- Target :`
14			`-- Dependency : ieee.std_logic_1164`
15			`-------------------------------------------------------------------------------`
16			`-- Description: Wishbone bus interface`
17			`-------------------------------------------------------------------------------`
18			`-- Copyright (c) 2001 Jamil Khatib`
19			`--`
20			`-- This VHDL design file is an open design; you can redistribute it and/or`
21			`-- modify it and/or implement it after contacting the author`
22			`-- You can check the draft license at`
23			`-- http://www.opencores.org/OIPC/license.shtml`
24
25			`-------------------------------------------------------------------------------`
26			`-- Revisions :`
27			`-- Revision Number : 1`
28			`-- Version : 0.1`
29			`-- Date : 11 April 2001`
30			`-- Modifier : Jamil Khatib (khatib@ieee.org)`
31			`-- Desccription : Created`
32			`-- ToOptimize :`
33			`-- Bugs :`
34			`-------------------------------------------------------------------------------`
35			`-- $Log: not supported by cvs2svn $`
36			`-- Revision 1.3 2001/04/27 18:21:59 jamil`
37			`-- After Prelimenray simulation`
38			`--`
39			`-- Revision 1.2 2001/04/22 20:08:16 jamil`
40			`-- Top level simulation`
41			`--`
42			`-------------------------------------------------------------------------------`
43			`LIBRARY ieee;`
44			`USE ieee.std_logic_1164.ALL;`
45
46			`ENTITY WB_IF_ent IS`
47			`GENERIC (`
48			`ADD_WIDTH : integer := 7); -- Address width`
49
50			`PORT (`
51			`-- WB Bus ports`
52			`CLK_I : IN std_logic; -- System Clock`
53			`RST_I : IN std_logic; -- System Reset`
54			`ACK_O : OUT std_logic; -- acknowledge`
55			`ADR_I : IN std_logic_vector(2 DOWNTO 0); -- address`
56			`CYC_I : IN std_logic; -- Bus cycle`
57			`DAT_I : IN std_logic_vector(31 DOWNTO 0); -- Input data`
58			`DAT_O : OUT std_logic_vector(31 DOWNTO 0); -- Output data`
59			`RTY_O : OUT std_logic; -- retry`
60			`STB_I : IN std_logic; -- strobe`
61			`WE_I : IN std_logic; -- Write`
62			`TAG0_O : OUT std_logic; -- TAG0 (TxDone)`
63			`TAG1_O : OUT std_logic; -- TAG1_O (RxRdy)`
64
65			`-- Internal ports`
66			`-- Tx`
67			`TxEnable : OUT std_logic; -- TxEnable (Write Frame completed)`
68			`TxDone : IN std_logic; -- Transmission Done (Read Frame completed)`
69			`TxDataInBuff : OUT std_logic_vector(7 DOWNTO 0); -- Input Data`
70			`Txwr : OUT std_logic; -- Tx Write Buffer`
71			`TxAborted : IN std_logic; -- Aborted Frame`
72			`TxAbort : OUT std_logic; -- Abort Transmission`
73			`TxOverflow : IN std_logic; -- Tx Buffer Overflow`
74			`TxFCSen : OUT std_logic; -- FCS enable;`
75
76			`-- Rx`
77			`RxFrameSize : IN std_logic_vector(ADD_WIDTH-1 DOWNTO 0); -- Frame Length`
78			`RxRdy : IN std_logic; -- Rx Ready`
79			`RxDataBuffOut : IN std_logic_vector(7 DOWNTO 0); -- Output Rx Buffer`
80			`RxOverflow : IN std_logic; -- Rx Buffer Overflow`
81			`RxFrameError : IN std_logic; -- Frame Error`
82			`RxFCSErr : IN std_logic; -- Rx FCS Error`
83			`RxRd : OUT std_logic; -- Rx Read data`
84			`RxAbort : IN std_logic -- Received Abort signal`
85
86			`);`
87
88			`END WB_IF_ent;`
89
90			`ARCHITECTURE WB_IF_rtl OF WB_IF_ent IS`
91			`SIGNAL ack_0 : std_logic; -- ack Reg 0`
92			`SIGNAL ack_1 : std_logic; -- ack Reg 1`
93			`SIGNAL ack_2 : std_logic; -- ack Reg 2`
94			`SIGNAL ack_3 : std_logic; -- ack Reg 3`
95			`SIGNAL ack_4 : std_logic; -- ack Reg 4`
96
97			`SIGNAL DATO_0 : std_logic_vector(31 DOWNTO 0); -- data out 0`
98			`SIGNAL DATO_1 : std_logic_vector(31 DOWNTO 0); -- data out 1`
99			`SIGNAL DATO_2 : std_logic_vector(31 DOWNTO 0); -- data out 2`
100			`SIGNAL DATO_3 : std_logic_vector(31 DOWNTO 0); -- data out 3`
101			`SIGNAL DATO_4 : std_logic_vector(31 DOWNTO 0); -- data out 4`
102
103			`SIGNAL en_0 : std_logic; -- Enable reg 0`
104			`SIGNAL en_1 : std_logic; -- Enable reg 1`
105			`SIGNAL en_2 : std_logic; -- Enable reg 2`
106			`SIGNAL en_3 : std_logic; -- Enable reg 3`
107			`SIGNAL en_4 : std_logic; -- Enable reg 4`
108
109			`SIGNAL counter : integer RANGE 0 TO 7; -- System counter`
110			`SIGNAL rst_count : std_logic; -- Reset counter`
111
112			`BEGIN -- WB_IF_rtl`
113
114			`-- purpose: WB fsm`
115			`-- type : sequential`
116			`-- inputs : CLK_I, RST_I`
117			`-- outputs:`
118			`WB_fsm : PROCESS (CLK_I, RST_I)`
119
120			`BEGIN -- PROCESS WB_fsm`
121			`IF (CLK_I'event AND CLK_I = '1') THEN`
122			`RTY_O <= '0';`
123
124			`IF (RST_I = '1') THEN -- synchronous reset`
125
126			`ACK_O <= '0';`
127			`DAT_O <= (OTHERS => '0');`
128			`RTY_O <= '0';`
129			`TAG0_O <= '0';`
130			`TAG1_O <= '0';`
131
132			`en_0 <= '0';`
133			`en_1 <= '0';`
134			`en_2 <= '0';`
135			`en_3 <= '0';`
136			`en_4 <= '0';`
137			`rst_count <= '1';`
138
139			`ELSE`
140			`TAG0_O <= TxDone;`
141			`TAG1_O <= RxRdy;`
142
143			`IF (CYC_I = '1' AND STB_I = '1') THEN`
144
145			`CASE ADR_I IS`
146			`WHEN "000" => -- Tx_SC`
147			`ACK_O <= ack_0;`
148			`DAT_O <= DATO_0;`
149
150			`en_0 <= '1';`
151			`en_1 <= '0';`
152			`en_2 <= '0';`
153			`en_3 <= '0';`
154			`en_4 <= '0';`
155			`rst_count <= '1';`
156
157			`WHEN "001" => -- Tx_Buff`
158			`ACK_O <= ack_1;`
159			`DAT_O <= DATO_1;`
160
161			`en_0 <= '0';`
162			`en_1 <= '1' and not ack_1;`
163			`en_2 <= '0';`
164			`en_3 <= '0';`
165			`en_4 <= '0';`
166
167			`IF counter = 4 THEN`
168			`rst_count <= '1';`
169			`else`
170			`rst_count <= '0';`
171			`END IF;`
172
173			`WHEN "010" => -- Rx_SC`
174			`ACK_O <= ack_2;`
175			`DAT_O <= DATO_2;`
176
177			`en_0 <= '0';`
178			`en_1 <= '0';`
179			`en_2 <= '1';`
180			`en_3 <= '0';`
181			`en_4 <= '0';`
182
183			`WHEN "011" => -- Rx_Buff`
184			`ACK_O <= ack_3;`
185			`DAT_O <= DATO_3;`
186
187			`en_0 <= '0';`
188			`en_1 <= '0';`
189			`en_2 <= '0';`
190			`en_3 <= '1' and not ack_3;`
191			`en_4 <= '0';`
192
193			`IF counter = 7 THEN`
194			`rst_count <= '1';`
195			`else`
196			`rst_count <= '0';`
197			`END IF;`
198
199			`WHEN "100" => -- Rx_len`
200			`ACK_O <= ack_4;`
201			`DAT_O <= DATO_4;`
202
203			`en_0 <= '0';`
204			`en_1 <= '0';`
205			`en_2 <= '0';`
206			`en_3 <= '0';`
207			`en_4 <= '1';`
208
209			`WHEN OTHERS =>`
210			`DAT_O <= (OTHERS => '0');`
211			`ACK_O <= '1';`
212
213			`en_0 <= '0';`
214			`en_1 <= '0';`
215			`en_2 <= '0';`
216			`en_3 <= '0';`
217			`en_4 <= '0';`
218
219			`END CASE;`
220
221			`ELSE`
222
223			`DAT_O <= (OTHERS => '0');`
224			`ACK_O <= '0';`
225
226			`en_0 <= '0';`
227			`en_1 <= '0';`
228			`en_2 <= '0';`
229			`en_3 <= '0';`
230			`en_4 <= '0';`
231
232			`END IF; -- cycle`
233
234			`END IF; --clock`
235
236			`END IF; -- reset`
237
238			`END PROCESS WB_fsm;`
239
240			`-------------------------------------------------------------------------------`
241			`-- purpose: Register0`
242			`-- type : sequential`
243			`-- inputs : CLK_I, RST_I`
244			`-- outputs:`
245			`reg0 : PROCESS (CLK_I, RST_I)`
246
247			`BEGIN -- PROCESS reg0`
248			`IF (CLK_I'event AND CLK_I = '1') THEN`
249
250			`IF (RST_I = '1') THEN`
251			`ack_0 <= '0';`
252			`DATO_0 <= (OTHERS => '0');`
253			`TxEnable <= '0';`
254			`TxAbort <= '0';`
255			`TxFCSen <= '1';`
256
257			`ELSE`
258			`DATO_0 <= "000000000000000000000000"&`
259			`"00" & '0'& TxOverflow & TxAborted & "00" & TxDone;`
260			`ack_0 <= en_0;`
261
262			`IF (en_0 = '1' AND WE_I = '1') THEN`
263
264			`TxEnable <= DAT_I(1);`
265			`TxAbort <= DAT_I(2);`
266			`TxFCSen <= DAT_I(5);`
267
268			`END IF; -- Write and en_0`
269
270
271			`END IF; -- rst`
272			`END IF; -- clk`
273
274			`END PROCESS reg0;`
275			`-------------------------------------------------------------------------------`
276			`-- purpose: Register1`
277			`-- type : sequential`
278			`-- inputs : CLK_I, RST_I`
279			`-- outputs:`
280			`reg1 : PROCESS (CLK_I, RST_I)`
281
282			`-- VARIABLE counter : integer RANGE 0 TO 3; -- Internal counter`
283
284			`BEGIN -- PROCESS reg1`
285			`IF (CLK_I'event AND CLK_I = '1') THEN`
286
287			`IF (RST_I = '1') THEN`
288			`ack_1 <= '0';`
289			`DATO_1 <= (OTHERS => '0');`
290			`-- counter := 0;`
291
292			`ELSE -- reset`
293			`DATO_1 <= (OTHERS => '0');`
294
295			`IF (WE_I = '1' AND en_1 = '1') THEN`
296
297			`-- Txwr <= '1';`
298			`CASE counter IS`
299			`WHEN 0 =>`
300			`Txwr <= '1';`
301			`TxDataInBuff <= DAT_I(7 DOWNTO 0);`
302			`ack_1 <= '0';`
303			`-- counter := counter + 1;`
304			`WHEN 1 =>`
305			`Txwr <= '1';`
306			`TxDataInBuff <= DAT_I(15 DOWNTO 8);`
307			`ack_1 <= '0';`
308			`-- counter := counter + 1;`
309			`WHEN 2 =>`
310			`Txwr <= '1';`
311			`TxDataInBuff <= DAT_I(23 DOWNTO 16);`
312			`ack_1 <= '0';`
313			`-- counter := counter + 1;`
314			`WHEN 3 =>`
315			`Txwr <= '1';`
316			`TxDataInBuff <= DAT_I(31 DOWNTO 24);`
317			`ack_1 <= '1';`
318			`-- counter := 0;`
319			`WHEN OTHERS =>`
320			`Txwr <= '0';`
321			`TxDataInBuff <= (others=> '0');`
322			`ack_1 <= '0';`
323			`END CASE;`
324
325			`ELSE -- WE_I`
326
327			`TxDataInBuff <= (OTHERS => '0');`
328			`-- counter := 0;`
329			`Txwr <= '0';`
330			`ack_1 <= '0';`
331			`END IF; -- WE_I and en_1`
332
333
334			`END IF; -- rst`
335			`END IF; -- clk`
336
337			`END PROCESS reg1;`
338
339			`-------------------------------------------------------------------------------`
340			`-- purpose: Register2`
341			`-- type : sequential`
342			`-- inputs : CLK_I, RST_I`
343			`-- outputs:`
344			`reg2 : PROCESS (CLK_I, RST_I)`
345
346			`BEGIN -- PROCESS reg3`
347			`IF (CLK_I'event AND CLK_I = '1') THEN`
348
349			`IF (RST_I = '1') THEN`
350			`ack_2 <= '0';`
351			`DATO_2 <= (OTHERS => '0');`
352
353			`ELSE`
354			`DATO_2 <= "000000000000000000000000"&`
355			`"000"& RxOverflow & RxAbort & RxFrameError & RxFCSErr & RxRdy;`
356			`ack_2 <= en_2;`
357
358			`END IF; -- rst`
359			`END IF; -- clk`
360
361			`END PROCESS reg2;`
362			`-------------------------------------------------------------------------------`
363			`-- purpose: Register3`
364			`-- type : sequential`
365			`-- inputs : CLK_I, RST_I`
366			`-- outputs:`
367			`reg3 : PROCESS (CLK_I, RST_I)`
368
369			`-- VARIABLE count : integer RANGE 0 TO 5; -- Internal counter`
370
371			`BEGIN -- PROCESS reg1`
372			`IF (CLK_I'event AND CLK_I = '1') THEN`
373
374			`IF (RST_I = '1') THEN`
375			`ack_3 <= '0';`
376			`DATO_3 <= (OTHERS => '0');`
377			`-- count := 0;`
378
379			`ELSE`
380
381			`IF (en_3 = '1' AND WE_I = '0') THEN`
382
383			`-- if (WE_I = '0') then`
384
385			`CASE counter IS`
386			`WHEN 0 =>`
387			`RxRd <= '1';`
388			`DATO_3 <= (OTHERS => '0');`
389			`ack_3 <= '0';`
390			`-- count := count + 1;`
391
392			`WHEN 1 =>`
393			`RxRd <= '1';`
394			`-- DATO_3 <= "000000000000000000000000" & RxDataBuffOut;`
395			`DATO_3 <= RxDataBuffOut & DATO_3(31 downto 8);`
396			`-- DATO_3 <= (OTHERS => '0');`
397			`ack_3 <= '0';`
398			`-- count := count + 1;`
399
400			`WHEN 2 =>`
401			`RxRd <= '1';`
402			`DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);`
403			`ack_3 <= '0';`
404			`-- count := count + 1;`
405
406			`WHEN 3 =>`
407			`RxRd <= '0';`
408
409			`DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);`
410			`ack_3 <= '0';`
411			`-- count := count + 1;`
412			`WHEN 4 =>`
413			`RxRd <= '0';`
414
415			`DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);`
416			`ack_3 <= '0';`
417			`-- count := count +1;`
418			`WHEN 5 =>`
419			`RxRd <= '0';`
420
421			`DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);`
422			`ack_3 <= '1';`
423			`---- count := 0;`
424
425			`WHEN OTHERS =>`
426			`RxRd <= '0';`
427
428			`DATO_3 <= (others=>'0');`
429			`ack_3 <= '0';`
430			`END CASE;`
431
432			`-- else`
433			`-- DATO_3 <= (others => '0');`
434			`-- counter := 0;`
435			`-- RxRd <= '0';`
436			`-- ack_3 <= '0';`
437
438			`-- end if; -- Write`
439
440			`ELSE`
441			`DATO_3 <= (OTHERS => '0');`
442			`-- count := 0;`
443			`RxRd <= '0';`
444			`ack_3 <= '0';`
445
446			`END IF; -- en`
447
448			`END IF; -- rst`
449			`END IF; -- clk`
450
451			`END PROCESS reg3;`
452
453			`-----------------------------------------------------------------------------`
454			`-- purpose: Register4`
455			`-- type : sequential`
456			`-- inputs : CLK_I, RST_I`
457			`-- outputs:`
458			`reg4 : PROCESS (CLK_I, RST_I)`
459
460			`BEGIN -- PROCESS reg4`
461			`IF (CLK_I'event AND CLK_I = '1') THEN`
462
463			`IF (RST_I = '1') THEN`
464			`ack_4 <= '0';`
465			`DATO_4 <= (OTHERS => '0');`
466
467			`ELSE`
468			`DATO_4 <= "000000000000000000000000"&`
469			`'0' & RxFrameSize;`
470			`ack_4 <= en_4;`
471
472			`END IF; -- rst`
473			`END IF; -- clk`
474
475			`END PROCESS reg4;`
476			`-----------------------------------------------------------------------------`
477
478			`-- purpose: system counter`
479			`-- type : sequential`
480			`-- inputs : CLK_I`
481			`-- outputs:`
482			`sys_counter : PROCESS (CLK_I)`
483			`BEGIN -- process sys_counter`
484
485			`IF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge`
486
487			`IF rst_count = '1' THEN`
488
489			`counter <= 0;`
490
491			`ELSIF en_1 = '1' OR en_3 = '1' THEN`
492
493			`counter <= counter +1;`
494
495			`ELSE`
496			`counter <= 0;`
497			`END IF;`
498			`END IF;`
499			`END PROCESS sys_counter;`
500			`-----------------------------------------------------------------------------`
501
502			`END WB_IF_rtl;`