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URL https://opencores.org/ocsvn/hdlc/hdlc/trunk

Subversion Repositories hdlc

[/] [hdlc/] [trunk/] [CODE/] [TOP/] [scripts/] [model/] [build_hdlc_top.do] - Blame information for rev 17

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Line No. Rev Author Line
1 10 khatib
vlib work
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vlib utility
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vlib hdlc
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vlib memLib
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vmap work
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vmap utility
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vmap hdlc
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vmap memLib
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# Utility files
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vcom -work utility  ../code/tools_pkg.vhd
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#memLib
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vcom -work memLib ../code/spmem.vhd
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vcom -work memLib  ../code/mem_pkg.vhd
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#HDLC files
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vcom -work hdlc  ../code/libs/PCK_CRC16_D8.vhd
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vcom -work hdlc  ../code/libs/hdlc_components_pkg.vhd
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#Work files
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#Rx
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vcom -work work  ../code/TOP/core/RxFCS.vhd
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vcom -work work  ../code/TOP/core/RxBuff.vhd -explicit
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vcom -work work  ../code/Rx/core/Zero_detect.vhd
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vcom -work work  ../code/Rx/core/flag_detect.vhd
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vcom -work work  ../code/Rx/core/Rxcont.vhd
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vcom -work work  ../code/Rx/core/RxChannel.vhd
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vcom -work work  ../code/TOP/core/RxSync.vhd
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#Tx
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vcom -work work  ../code/TOP/core/TxFCS.vhd
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vcom -work work  ../code/TOP/core/TxBuff.vhd -explicit
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vcom -work work  ../code/Tx/core/flag_ins.vhd
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vcom -work work  ../code/Tx/core/zero_ins.vhd
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vcom -work work  ../code/Tx/core/TXcont.vhd
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vcom -work work  ../code/Tx/core/TxChannel.vhd
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vcom -work work  ../code/TOP/core/TxSync.vhd
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#WB and host
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vcom -work work  ../code/TOP/core/WB_IF.vhd
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vcom -work work  ../code/TOP/core/hdlc.vhd
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# Test bench
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vcom -work work  ../code/TOP/tb/hdlc_tb.vhd -explicit
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