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[/] [hdlc/] [trunk/] [CODE/] [TX/] [tb/] [tx_tb.vhd] - Blame information for rev 17

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1 8 khatib
-------------------------------------------------------------------------------
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-- Title      :  Tx Channel test bench
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-- Project    :  HDLC controller
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-------------------------------------------------------------------------------
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-- File        : tx_tb.vhd
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-- Author      : Jamil Khatib  (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Created     :2001/01/16
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-- Last update: 2001/01/26
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-- Platform    : 
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-- Simulators  : Modelsim 5.3XE/Windows98
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-- Synthesizers: 
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-- Target      : 
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-- Dependency  : ieee.std_logic_1164
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--
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-------------------------------------------------------------------------------
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-- Description:  Transmit Channel test bench
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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-- 
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1
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-- Version         :   0.1
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-- Date            :   16 Jan 2001
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Created
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-- ToOptimize      :
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-- Bugs            :   
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library hdlc;
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use hdlc.hdlc_components_pkg.all;
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entity tx_tb_ent is
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end tx_tb_ent;
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architecture tx_tb_beh of tx_tb_ent is
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  type streem is array (0 to 3) of std_logic_vector(7 downto 0);
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  constant dataStreem : streem := ("10010110", "11111111", "01101101", "10010011");
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  signal TxClk        : std_logic := '0';  -- System clock
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  signal rst_n        : std_logic := '0';  -- system reset
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  signal TXEN         : std_logic;      -- TX enable
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  signal TX           : std_logic;      -- Transmit serial data
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  signal ValidFrame   : std_logic := '0';  -- ValidFrame
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  signal AbortFrame   : std_logic;      -- Abort Frame
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  signal AbortedTrans : std_logic;      -- Aborted transmission
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  signal WriteByte    : std_logic := '0';  -- Backend Write byte
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  signal rdy          : std_logic;      -- Backend Ready
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  signal TxData       : std_logic_vector(7 downto 0);  -- Backend data bus
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begin  -- tx_tb_beh
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  uut : TxChannel_ent
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    port map (
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      TxClk        => TxClk,
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      rst_n        => rst_n,
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      TXEN         => TXEN,
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      Tx           => Tx,
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      ValidFrame   => ValidFrame,
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      AbortFrame   => AbortFrame,
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      AbortedTrans => AbortedTrans,
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      WriteByte    => WriteByte,
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      rdy          => rdy,
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      TxData       => TxData);
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-------------------------------------------------------------------------------
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  Txclk <= not Txclk after 20 ns;
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  rst_n <= '0',
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           '1' after 30 ns;
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  TxEn <= '1';                          --,
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--          '0' after 960 ns,
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--          '1' after 1280 ns;
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  AbortFrame <= '0';
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-------------------------------------------------------------------------------
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  -- purpose: Serial Interface
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  -- type   : sequential
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  -- inputs : TxClk, rst
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  -- outputs: 
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  Serial_Interface   : process (TxClk, rst_n)
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    variable output  : std_logic_vector(7 downto 0) := "00000000";
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                                                           -- Output regieter
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    variable counter : integer                      := 0;  -- Counter
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  begin  -- process Serial Interface
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    if rst_n = '0' then                 -- asynchronous reset (active low)
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      output  := (others => '0');
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      Counter := 0;
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    elsif TxClk'event and TxClk = '1' then  -- rising clock edge
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      output  := TX & output(7 downto 1);
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      Counter := Counter +1;
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      if counter = 7 then
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        counter := 0;
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      end if;
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    end if;
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  end process Serial_Interface;
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-----------------------------------------------------------------------------
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-- purpose: Backend process
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-- type   : combinational
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-- inputs : 
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-- outputs: 
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  backend_proc       : process
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    variable counter : integer := 6;    -- counter
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  begin  -- process backend_proc
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    for i in 0 to dataStreem'length-1 loop
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      if counter = 6 then
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        ValidFrame <= '0' after 330 ns,
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                      '1' after 640 ns;
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        counter    := 0;
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      end if;
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      wait until rdy = '1';
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      WriteByte <= '1' after 30 ns;
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      TxData <= dataStreem(i);
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      counter := counter +1;
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      wait until rdy = '0';
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      WriteByte <= '0' after 10 ns;
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    end loop;  -- i
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  end process backend_proc;
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--Used to check the Abort Condition
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--  WriteByte <= '1' after 730 ns,
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--               '0' after 750 ns,
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--               '1' after 1310 ns,
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--               '0' after 1340 ns,
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--               '1' after 1980 ns,
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--               '0' after 2000 ns;
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end tx_tb_beh;

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