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[/] [hdlc/] [trunk/] [DOCS/] [hdlc_features.txt] - Blame information for rev 17
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khatib |
HDLC controller initial features:
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1. 8 bit parallel backend interface
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2. use external RX and TX clocks
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3. Start and end of frame pattern generation
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4. Start and end of frame pattern checking
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5. Idle pattern generation and detection (all ones)
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5. a) Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
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6. Zero insertion
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7. Abort pattern generation and checking
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8. Address insertion and detection by software
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9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used )
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10. FIFO buffers and synchronization (External)
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11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
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12. Q.921 compliant(???)
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