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\documentclass[a4paper,11pt]{article}
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\usepackage{fancyheadings}
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\usepackage{lastpage}
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\pagestyle{fancy}
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%% defined commands
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\newcommand{\openhw}{\mbox{\textbf{\textit{OpenHW}}}}
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\newcommand{\opendesign}{\mbox{\textbf{\textit{OpenDesign}}}}
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\newcommand{\openipcore}{\mbox{\textbf{\textit{OpenIPCore}}}}
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\newcommand{\opencores}{\mbox{\textbf{\textit{OpenCores}}}}
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%% addcomment command: Author name: Comments
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\newcommand{\addcomment}[2]{\rule{1ex}{1ex} \emph{Comment by \textbf{#1}: #2 }\rule{1ex}{1ex}}
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%% addauthor command: Author name : List of changes: date: contact address
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\newcommand{\addauthor}[4]{#1 & #2 & #3 & #4 \\ \hline}
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%% Optional suffix or prefix
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\newcommand{\prefix}[1]{[\textit{#1\_}]}
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\newcommand{\suffix}[1]{[\textit{\_#1}]}
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%% Must define Project Name
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%% Must define Author Name
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\author{Jamil Khatib}
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\title{HDLC controller core}
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%% Hyphenation list %%
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\hyphenation{OpenIP OpenIPCore OpenHW OpenDesign OpenCores ISP CPLD FPGA CAD VHDL hard-ware soft-ware DSP ASIC}
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%%Headers & footers
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\lhead{\uppercase\rightmark}
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\chead{}
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\rhead{\bfseries \opencores Project}
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\lfoot{HDLC controller}
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\cfoot{}
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\rfoot{\thepage~ of \pageref{LastPage}}
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\setlength{\headrulewidth}{0.4pt}
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\setlength{\footrulewidth}{0.4pt}
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%% begin Document
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\begin{document}
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%% Cover page
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\maketitle
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\begin{center}(C) Copyright 2001 Jamil Khatib.\end{center}
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\thispagestyle{empty}
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\newpage
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%%Table of contents page
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\tableofcontents
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\newpage
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\section{List of authors and changes}
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\begin{tabular}{|l|l|l|l|l|}
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\hline
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Name & Changes & Date & Contact address\\
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\hline
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\hline
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\addauthor{Jamil Khatib}{Initial release}{9-1-2001}{khatib@ieee.org}
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%% use add author command here
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\end{tabular}
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\newpage
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%%- New section -%%
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%%------------------------------------------%%
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\section{Project Definition}
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\subsection{Introduction}
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HDLC protocol is used as a data link of most of the current communication systems like ISDN, Frame Relay, Ethernet \dots HDLC is a family of protocols that varies in address size, control field and FCS.
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%\subsection{Definition}
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\subsection{Objectives}
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The aim of this project is to develop the basic HDLC functionalities to be used by many communication systems.
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%%- New section -%%
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%%------------------------------------------%%
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\section{Specifications}
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\subsection{System Specification}
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\begin{itemize}
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\item 1. 8 bit parallel back-end interface
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\item 2. Use external RX and TX clocks
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\item 3. Start and end of frame pattern generation
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\item 4. Start and end of frame pattern checking
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\item 5. Idle pattern generation and detection (all ones)
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\item 5. a) Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
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\item 6. Zero insertion
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\item 7. Abort pattern generation and checking
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\item 8. Address insertion and detection by software
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\item 9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used )
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\item 10. FIFO buffers and synchronization (External)
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\item 11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
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\item 12. Q.921 compliant
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\end{itemize}
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\subsection{External Interfaces}
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\subsubsection{Receive Channel}
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\begin{tabular}{|l|l|l|}
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\hline
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Signal name& Direction& Description\\
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\hline
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\hline
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Serial Interface & & \\
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\hline
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\hline
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RxClk & Input & Receive Clock\\
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Rx & Input& Receive Data\\
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\hline
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\hline
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Back-end Interface & &\\
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\hline
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\hline
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RxD[7:0]& Output& Receive data bus\\
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Valid Frame& Output& Valid Frame indication during all frame bytes transfer\\
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Frame Error& Output& Error in the received data (lost bits)\\
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Aborted& Output& Aborted Frame\\
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Read& input& Read byte\\
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Ready& Output& Valid data exists\\
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\hline
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\end{tabular}
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\subsubsection{Back-end interface mapping to Wishbone SoC bus}
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\begin{tabular}{|l|l|}
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\hline
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Signal Name& Wishbone signal\\
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\hline
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\hline
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Master Configuration connected to FIFO&\\
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\hline
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Data[7:0]& DAT\_O[7:0]\\
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ValidFrame& STB\_O\\
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ReadByte& ACK\_I and not RTY\_I\\
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ready& WE\_O\\
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FrameERR& TAG\_O[0]\\
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Aborted& TAG\_O[1]\\
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\hline
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Slave FIFO(two-clock domain FIFO)&\\
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\hline
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Data[7:0]& DAT\_I[7:0]\\
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Chip Select& STB\_I\\
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STB\_I& ACK\_O\\
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FullFlag& RTY\_O\\
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Write& WE\_I\\
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\hline
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Slave Configuration &\\
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\hline
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Data[7:0]& DAT\_O[7:0]\\
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ValidFrame& TAG\_O[0]\\
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ReadByte& WE\_I\\
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Ready& RTY\_O\\
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Always active& ACK\_O\\
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FrameERR& TAG\_O[1]\\
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Aborted& TAG\_O[0]\\
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\hline
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\end{tabular}
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\subsubsection{Transmit Channel}
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%%- New section -%%
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%%------------------------------------------%%
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\section{Internal Blocks}
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%%- New section -%%
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%%------------------------------------------%%
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\section{Design description}
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\subsection{Design notes}
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\subsection{Timing}
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\subsection{Diagrams}
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%%- New section -%%
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%%------------------------------------------%%
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\section{Testing and verifications}
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\begin{tabular}{|l|l|l|}
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\hline
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Requirement & Test method & Validation method \\
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\hline
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\hline
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Interface timing & &\\
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\hline
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& & \\
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\hline
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\hline
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Functionality & & \\
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\hline
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\end{tabular}
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\subsection{Simulation and Test benches}
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\subsection{Verification techniques and algorithms}
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\subsection{Test plans}
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%%- New section -%%
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%%------------------------------------------%%
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\section{Implementations}
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\subsection{Scripts, files and any other information}
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\subsection{Design conventions and coding styles}
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%%- New section -%%
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%%------------------------------------------%%
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\section{Reviews and comments}
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%%- New section -%%
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%%------------------------------------------%%
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\section{References}
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\end{document}
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