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\documentclass[a4paper,11pt]{article}
\usepackage{fancyheadings}
\usepackage{lastpage}
\pagestyle{fancy}
 
%% defined commands
\newcommand{\openhw}{\mbox{\textbf{\textit{OpenHW}}}}
\newcommand{\opendesign}{\mbox{\textbf{\textit{OpenDesign}}}}
\newcommand{\openipcore}{\mbox{\textbf{\textit{OpenIPCore}}}}
\newcommand{\opencores}{\mbox{\textbf{\textit{OpenCores}}}}
 
%% addcomment command: Author name: Comments
\newcommand{\addcomment}[2]{\rule{1ex}{1ex} \emph{Comment by \textbf{#1}: #2 }\rule{1ex}{1ex}}
 
%% addauthor command: Author name : List of changes: date: contact address
\newcommand{\addauthor}[4]{#1 & #2 & #3 & #4 \\ \hline}
 
 
 
%% Optional suffix or prefix
\newcommand{\prefix}[1]{[\textit{#1\_}]}
\newcommand{\suffix}[1]{[\textit{\_#1}]}
 
 
%% Must define Project Name
%% Must define Author Name
 
\author{Jamil Khatib}
\title{HDLC controller core}
 
 
 
%% Hyphenation list %%
\hyphenation{OpenIP OpenIPCore OpenHW OpenDesign OpenCores ISP CPLD FPGA CAD VHDL hard-ware soft-ware DSP ASIC}
 
 
%%Headers & footers
\lhead{\uppercase\rightmark}
\chead{}
\rhead{\bfseries \opencores Project}
\lfoot{HDLC controller}
\cfoot{}
\rfoot{\thepage~ of \pageref{LastPage}}
\setlength{\headrulewidth}{0.4pt}
\setlength{\footrulewidth}{0.4pt}
 
%% begin Document
\begin{document}
%% Cover page
\maketitle
 
\begin{center}(C) Copyright 2001 Jamil Khatib.\end{center}
 
\thispagestyle{empty}
 
\newpage
 
 
%%Table of contents page
\tableofcontents
 
\newpage
 
\section{List of authors and changes}
 
\begin{tabular}{|l|l|l|l|l|}
\hline
Name & Changes & Date & Contact address\\
\hline
\hline
 
\addauthor{Jamil Khatib}{Initial release}{9-1-2001}{khatib@ieee.org}
%% use add author command here
 
 
\end{tabular}
 
\newpage
 
%%- New section -%%
%%------------------------------------------%%
\section{Project Definition}
 
\subsection{Introduction}
HDLC protocol is used as a data link of most of the current communication systems like ISDN, Frame Relay, Ethernet \dots HDLC is a family of protocols that varies in address size, control field and FCS.
 
%\subsection{Definition}
 
\subsection{Objectives}
The aim of this project is to develop the basic HDLC functionalities to be used by many communication systems.
 
 
%%- New section -%%
%%------------------------------------------%%
\section{Specifications}
 
\subsection{System Specification}
\begin{itemize}
\item 1. 8 bit parallel back-end interface
\item 2. Use external RX and TX clocks
\item 3. Start and end of frame pattern generation
\item 4. Start and end of frame pattern checking
\item 5. Idle pattern generation and detection (all ones)
\item 5. a)  Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
\item 6. Zero insertion
\item 7. Abort pattern generation and checking
\item 8. Address insertion and detection by software
\item 9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used )
\item 10. FIFO buffers and synchronization (External)
\item 11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
\item 12. Q.921 compliant
\item 13. The core should not have internal configuration registers.
\end{itemize}
 
\subsection{External Interfaces}
 
\subsubsection{Receive Channel}
 
 
\begin{tabular}{|l|l|l|}
\hline
Signal name& Direction& Description\\
\hline
\hline
Control interface & & \\
\hline
\hline
Rst & Input & System asynchronous reset(active low)\\
\hline
\hline
Serial Interface & & \\
\hline
\hline
RxClk & Input & Receive Clock\\
Rx & Input& Receive Data\\
RxEn & Input & RX enable (active high)\\
\hline
\hline
Back-end Interface & &\\
\hline
\hline
RxD[7:0]& Output& Receive data bus\\
ValidFrame& Output& Valid Frame indication during all frame bytes transfer\\
FrameErr& Output& Error in the received data (lost bits)\\
Aborted& Output& Aborted Frame\\
Read& input& Read byte\\
Ready& Output& Valid data exists\\
\hline
\end{tabular}
 
\subsubsection{Back-end interface mapping to Wishbone SoC bus}
The HDLC receive backend interface can be used as a slave core or master according to the below mapping. The core supports SINGLE READ Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.
 
 
\begin{tabular}{|l|l|}
\hline
Signal Name& Wishbone signal\\
\hline
\hline
Master Configuration connected to FIFO&\\
\hline
RxClk & CLK\_I\\
Rst & not RST\_I\\
RxD[7:0]& DAT\_O(7:0)\\
ValidFrame& STB\_O\\
ValidFrame& CYC\_O\\
ReadByte& ACK\_I and not RTY\_I\\
Ready& WE\_O\\
FrameERR& TAG0\_O\\
Aborted& TAG1\_O\\
\hline
Slave FIFO(two-clock domain FIFO)&\\
\hline
Data[7:0]& DAT\_I(7:0)\\
Chip Select& STB\_I\\
Chip Select& CYC\_I\\
STB\_I& ACK\_O and not FullFlag\\
FullFlag& RTY\_O\\
Write& WE\_I\\
\hline
Slave Configuration &\\
\hline
RxClk & CLK\_I\\
Rst & not RST\_I\\
RxD[7:0]& DAT\_O(7:0)\\
ValidFrame& TAG0\_O\\
ReadByte& not WE\_I\\
Ready& not RTY\_O\\
STB\_I and not WR\_I& ACK\_O\\
FrameERR& TAG1\_O\\
Aborted& TAG2\_O\\
\hline
\end{tabular}
 
 
\subsubsection{Transmit Channel}
 
 
%%- New section -%%
%%------------------------------------------%%
\section{Internal Blocks}
 
 
%%- New section -%%
%%------------------------------------------%%
\section{Design description}
 
\subsection{Design notes}
\subsection{Timing}
\subsection{Diagrams}
 
 
 
%%- New section -%%
%%------------------------------------------%%
\section{Testing and verifications}
 
 
\begin{tabular}{|l|l|l|}
\hline
Requirement & Test method & Validation method \\
\hline
\hline
Interface timing & &\\
\hline
& & \\
\hline
\hline
Functionality & & \\
\hline
\end{tabular}
\subsection{Simulation and Test benches}
 
\subsection{Verification techniques and algorithms}
 
\subsection{Test plans}
 
%%- New section -%%
%%------------------------------------------%%
\section{Implementations}
 
\subsection{Scripts, files and any other information}
 
\subsection{Design conventions and coding styles}
 
%%- New section -%%
%%------------------------------------------%%
\section{Reviews and comments}
 
%%- New section -%%
%%------------------------------------------%%
\section{References}
 
 
\end{document}

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[/] [hdlc/] [trunk/] [DOCS/] [hdlc_project.tex] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	khatib	`\documentclass[a4paper,11pt]{article}`
2			`\usepackage{fancyheadings}`
3			`\usepackage{lastpage}`
4			`\pagestyle{fancy}`
5
6			`%% defined commands`
7			`\newcommand{\openhw}{\mbox{\textbf{\textit{OpenHW}}}}`
8			`\newcommand{\opendesign}{\mbox{\textbf{\textit{OpenDesign}}}}`
9			`\newcommand{\openipcore}{\mbox{\textbf{\textit{OpenIPCore}}}}`
10			`\newcommand{\opencores}{\mbox{\textbf{\textit{OpenCores}}}}`
11
12			`%% addcomment command: Author name: Comments`
13			`\newcommand{\addcomment}[2]{\rule{1ex}{1ex} \emph{Comment by \textbf{#1}: #2 }\rule{1ex}{1ex}}`
14
15			`%% addauthor command: Author name : List of changes: date: contact address`
16			`\newcommand{\addauthor}[4]{#1 & #2 & #3 & #4 \\ \hline}`
17
18
19
20			`%% Optional suffix or prefix`
21			`\newcommand{\prefix}[1]{[\textit{#1\_}]}`
22			`\newcommand{\suffix}[1]{[\textit{\_#1}]}`
23
24
25			`%% Must define Project Name`
26			`%% Must define Author Name`
27
28			`\author{Jamil Khatib}`
29			`\title{HDLC controller core}`
30
31
32
33			`%% Hyphenation list %%`
34			`\hyphenation{OpenIP OpenIPCore OpenHW OpenDesign OpenCores ISP CPLD FPGA CAD VHDL hard-ware soft-ware DSP ASIC}`
35
36
37			`%%Headers & footers`
38			`\lhead{\uppercase\rightmark}`
39			`\chead{}`
40			`\rhead{\bfseries \opencores Project}`
41			`\lfoot{HDLC controller}`
42			`\cfoot{}`
43			`\rfoot{\thepage~ of \pageref{LastPage}}`
44			`\setlength{\headrulewidth}{0.4pt}`
45			`\setlength{\footrulewidth}{0.4pt}`
46
47			`%% begin Document`
48			`\begin{document}`
49			`%% Cover page`
50			`\maketitle`
51
52			`\begin{center}(C) Copyright 2001 Jamil Khatib.\end{center}`
53
54			`\thispagestyle{empty}`
55
56			`\newpage`
57
58
59			`%%Table of contents page`
60			`\tableofcontents`
61
62			`\newpage`
63
64			`\section{List of authors and changes}`
65
66			`\begin{tabular}{\|l\|l\|l\|l\|l\|}`
67			`\hline`
68			`Name & Changes & Date & Contact address\\`
69			`\hline`
70			`\hline`
71
72			`\addauthor{Jamil Khatib}{Initial release}{9-1-2001}{khatib@ieee.org}`
73			`%% use add author command here`
74
75
76			`\end{tabular}`
77
78			`\newpage`
79
80			`%%- New section -%%`
81			`%%------------------------------------------%%`
82			`\section{Project Definition}`
83
84			`\subsection{Introduction}`
85			`HDLC protocol is used as a data link of most of the current communication systems like ISDN, Frame Relay, Ethernet \dots HDLC is a family of protocols that varies in address size, control field and FCS.`
86
87			`%\subsection{Definition}`
88
89			`\subsection{Objectives}`
90			`The aim of this project is to develop the basic HDLC functionalities to be used by many communication systems.`
91
92
93			`%%- New section -%%`
94			`%%------------------------------------------%%`
95			`\section{Specifications}`
96
97			`\subsection{System Specification}`
98			`\begin{itemize}`
99			`\item 1. 8 bit parallel back-end interface`
100			`\item 2. Use external RX and TX clocks`
101			`\item 3. Start and end of frame pattern generation`
102			`\item 4. Start and end of frame pattern checking`
103			`\item 5. Idle pattern generation and detection (all ones)`
104			`\item 5. a) Idle pattern is assumed only after the end of a frame which is signaled by an abort signal`
105			`\item 6. Zero insertion`
106			`\item 7. Abort pattern generation and checking`
107			`\item 8. Address insertion and detection by software`
108			`\item 9. CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used )`
109			`\item 10. FIFO buffers and synchronization (External)`
110			`\item 11. Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)`
111			`\item 12. Q.921 compliant`
112	6	khatib	`\item 13. The core should not have internal configuration registers.`
113	2	khatib	`\end{itemize}`
114
115			`\subsection{External Interfaces}`
116
117			`\subsubsection{Receive Channel}`
118
119
120			`\begin{tabular}{\|l\|l\|l\|}`
121			`\hline`
122			`Signal name& Direction& Description\\`
123			`\hline`
124			`\hline`
125	6	khatib	`Control interface & & \\`
126			`\hline`
127			`\hline`
128			`Rst & Input & System asynchronous reset(active low)\\`
129			`\hline`
130			`\hline`
131	2	khatib	`Serial Interface & & \\`
132			`\hline`
133			`\hline`
134			`RxClk & Input & Receive Clock\\`
135			`Rx & Input& Receive Data\\`
136	6	khatib	`RxEn & Input & RX enable (active high)\\`
137	2	khatib	`\hline`
138			`\hline`
139			`Back-end Interface & &\\`
140			`\hline`
141			`\hline`
142			`RxD[7:0]& Output& Receive data bus\\`
143	6	khatib	`ValidFrame& Output& Valid Frame indication during all frame bytes transfer\\`
144			`FrameErr& Output& Error in the received data (lost bits)\\`
145	2	khatib	`Aborted& Output& Aborted Frame\\`
146			`Read& input& Read byte\\`
147			`Ready& Output& Valid data exists\\`
148			`\hline`
149			`\end{tabular}`
150
151			`\subsubsection{Back-end interface mapping to Wishbone SoC bus}`
152	6	khatib	`The HDLC receive backend interface can be used as a slave core or master according to the below mapping. The core supports SINGLE READ Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.`
153	2	khatib
154	6	khatib
155	2	khatib	`\begin{tabular}{\|l\|l\|}`
156			`\hline`
157			`Signal Name& Wishbone signal\\`
158			`\hline`
159			`\hline`
160			`Master Configuration connected to FIFO&\\`
161			`\hline`
162	6	khatib	`RxClk & CLK\_I\\`
163			`Rst & not RST\_I\\`
164			`RxD[7:0]& DAT\_O(7:0)\\`
165	2	khatib	`ValidFrame& STB\_O\\`
166	6	khatib	`ValidFrame& CYC\_O\\`
167	2	khatib	`ReadByte& ACK\_I and not RTY\_I\\`
168	6	khatib	`Ready& WE\_O\\`
169			`FrameERR& TAG0\_O\\`
170			`Aborted& TAG1\_O\\`
171	2	khatib	`\hline`
172			`Slave FIFO(two-clock domain FIFO)&\\`
173			`\hline`
174	6	khatib	`Data[7:0]& DAT\_I(7:0)\\`
175	2	khatib	`Chip Select& STB\_I\\`
176	6	khatib	`Chip Select& CYC\_I\\`
177			`STB\_I& ACK\_O and not FullFlag\\`
178	2	khatib	`FullFlag& RTY\_O\\`
179			`Write& WE\_I\\`
180			`\hline`
181			`Slave Configuration &\\`
182			`\hline`
183	6	khatib	`RxClk & CLK\_I\\`
184			`Rst & not RST\_I\\`
185			`RxD[7:0]& DAT\_O(7:0)\\`
186			`ValidFrame& TAG0\_O\\`
187			`ReadByte& not WE\_I\\`
188			`Ready& not RTY\_O\\`
189			`STB\_I and not WR\_I& ACK\_O\\`
190			`FrameERR& TAG1\_O\\`
191			`Aborted& TAG2\_O\\`
192	2	khatib	`\hline`
193			`\end{tabular}`
194
195
196			`\subsubsection{Transmit Channel}`
197
198
199			`%%- New section -%%`
200			`%%------------------------------------------%%`
201			`\section{Internal Blocks}`
202
203
204			`%%- New section -%%`
205			`%%------------------------------------------%%`
206			`\section{Design description}`
207
208			`\subsection{Design notes}`
209			`\subsection{Timing}`
210			`\subsection{Diagrams}`
211
212
213
214			`%%- New section -%%`
215			`%%------------------------------------------%%`
216			`\section{Testing and verifications}`
217
218
219			`\begin{tabular}{\|l\|l\|l\|}`
220			`\hline`
221			`Requirement & Test method & Validation method \\`
222			`\hline`
223			`\hline`
224			`Interface timing & &\\`
225			`\hline`
226			`& & \\`
227			`\hline`
228			`\hline`
229			`Functionality & & \\`
230			`\hline`
231			`\end{tabular}`
232			`\subsection{Simulation and Test benches}`
233
234			`\subsection{Verification techniques and algorithms}`
235
236			`\subsection{Test plans}`
237
238			`%%- New section -%%`
239			`%%------------------------------------------%%`
240			`\section{Implementations}`
241
242			`\subsection{Scripts, files and any other information}`
243
244			`\subsection{Design conventions and coding styles}`
245
246			`%%- New section -%%`
247			`%%------------------------------------------%%`
248			`\section{Reviews and comments}`
249
250			`%%- New section -%%`
251			`%%------------------------------------------%%`
252			`\section{References}`
253
254
255			`\end{document}`