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wzab |
-------------------------------------------------------------------------------
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-- Title : Top entity of heap-sorter
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-- Project : heap-sorter
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-------------------------------------------------------------------------------
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-- File : sorter_sys.vhd
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-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
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-- Company :
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-- Created : 2010-05-14
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-- Last update: 2011-07-11
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-- Platform :
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010 Wojciech M. Zabolotny
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-- This file is published under the BSD license, so you can freely adapt
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-- it for your own purposes.
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-- Additionally this design has been described in my article
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-- Additionally this design has been described in my article:
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-- Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
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-- for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
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-- I'd be glad if you cite this article when you publish something based
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-- on my design.
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2010-05-14 1.0 wzab Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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library work;
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use work.sorter_pkg.all;
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use work.sys_config.all;
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entity sorter_sys is
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generic (
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NLEVELS : integer := SYS_NLEVELS -- number of levels in the sorter heap
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);
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port (
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din : in T_DATA_REC;
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we : in std_logic;
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dout : out T_DATA_REC;
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dav : out std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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ready : out std_logic);
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end sorter_sys;
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architecture sorter_sys_arch1 of sorter_sys is
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component sort_dp_ram
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generic (
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ADDR_WIDTH : natural;
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NLEVELS : natural;
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NAME : string);
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port (
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clk : in std_logic;
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addr_a : in std_logic_vector(NLEVELS-1 downto 0);
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addr_b : in std_logic_vector(NLEVELS-1 downto 0);
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data_a : in T_DATA_REC;
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data_b : in T_DATA_REC;
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we_a : in std_logic;
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we_b : in std_logic;
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q_a : out T_DATA_REC;
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q_b : out T_DATA_REC);
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end component;
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component sorter_ctrl
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generic (
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NLEVELS : integer;
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NADDRBITS : integer);
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port (
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tm_din : in T_DATA_REC;
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tm_dout : out T_DATA_REC;
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tm_addr : out std_logic_vector(NLEVELS-1 downto 0);
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tm_we : out std_logic;
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lm_din : in T_DATA_REC;
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lm_dout : out T_DATA_REC;
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lm_addr : out std_logic_vector(NLEVELS-1 downto 0);
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lm_we : out std_logic;
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rm_din : in T_DATA_REC;
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rm_dout : out T_DATA_REC;
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rm_addr : out std_logic_vector(NLEVELS-1 downto 0);
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rm_we : out std_logic;
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up_in : in std_logic;
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up_in_val : in T_DATA_REC;
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up_in_addr : in std_logic_vector(NLEVELS-1 downto 0);
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up_out : out std_logic;
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up_out_val : out T_DATA_REC;
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up_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
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low_out : out std_logic;
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low_out_val : out T_DATA_REC;
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low_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
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low_in : in std_logic;
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low_in_val : in T_DATA_REC;
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low_in_addr : in std_logic_vector(NLEVELS-1 downto 0);
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clk : in std_logic;
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clk_en : in std_logic;
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ready_in : in std_logic;
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ready_out : out std_logic;
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rst_n : in std_logic);
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end component;
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-- Create signals for address buses
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-- Some of them will remain unused.
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subtype T_SORT_BUS_ADDR is std_logic_vector(NLEVELS-1 downto 0);
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type T_SORT_ADDR_BUSES is array (NLEVELS downto 0) of T_SORT_BUS_ADDR;
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signal low_addr, up_addr, addr_dr, addr_dl, addr_u : T_SORT_ADDR_BUSES := (others => (others => '0'));
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type T_SORT_DATA_BUSES is array (NLEVELS downto 0) of T_DATA_REC;
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signal up_update_path, low_update_path, data_d, data_dl, data_dr, data_u : T_SORT_DATA_BUSES := (others => DATA_REC_INIT_DATA);
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signal q_dr, q_dl, q_u, q_ul, q_ur : T_SORT_DATA_BUSES := (others => DATA_REC_INIT_DATA);
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signal we_ul, we_ur, we_u, we_dl, we_dr, low_update, up_update, s_ready : std_logic_vector(NLEVELS downto 0) := (others => '0');
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signal addr_switch, addr_switch_del : std_logic_vector(NLEVELS downto 0);
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signal l0_reg : T_DATA_REC;
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signal clk_en : std_logic := '1';
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begin -- sorter_sys_arch1
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-- Build the sorting tree
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g1 : for i in 0 to NLEVELS-1 generate
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-- Two RAMs from the upper level are seen as a single RAM
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-- We use the most significant bit (i-th bit) to distinguish RAM
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-- In all RAMs the A-ports are used for upstream connections
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-- and the B-ports are used for downstream connections
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-- Below are processes used to combine two upstream RAMs in a single one
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i0a : if i >= 1 generate
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addr_switch(i) <= addr_u(i)(i-1);
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end generate i0a;
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i0b : if i = 0 generate
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addr_switch(i) <= '0';
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end generate i0b;
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-- There is a problem with reading of data provided by two upstream RAMs
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-- we need to multiplex the data...
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-- Delay for read data multiplexer
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s1 : process (clk, rst_n)
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begin -- process s1
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if rst_n = '0' then -- asynchronous reset (active low)
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addr_switch_del(i) <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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addr_switch_del(i) <= addr_switch(i);
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end if;
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end process s1;
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-- Upper RAM signals' multiplexer
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c1 : process (addr_switch, addr_switch_del, q_ul, q_ur, we_u)
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begin -- process c1
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we_ul(i) <= '0';
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we_ur(i) <= '0';
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if addr_switch(i) = '1' then
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we_ul(i) <= we_u(i);
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else
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we_ur(i) <= we_u(i);
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end if;
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if addr_switch_del(i) = '1' then
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q_u(i) <= q_ul(i);
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else
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q_u(i) <= q_ur(i);
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end if;
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end process c1;
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dp_ram_l : sort_dp_ram
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generic map (
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NLEVELS => NLEVELS,
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ADDR_WIDTH => i,
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NAME => "L")
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port map (
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clk => clk,
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addr_a => addr_dl(i),
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addr_b => addr_u(i+1),
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data_a => data_dl(i),
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data_b => data_u(i+1),
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we_a => we_dl(i),
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we_b => we_ul(i+1),
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q_a => q_dl(i),
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q_b => q_ul(i+1));
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dp_ram_r : sort_dp_ram
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generic map (
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NLEVELS => NLEVELS,
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ADDR_WIDTH => i,
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NAME => "R")
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port map (
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clk => clk,
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addr_a => addr_dr(i),
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addr_b => addr_u(i+1),
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data_a => data_dr(i),
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data_b => data_u(i+1),
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we_a => we_dr(i),
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we_b => we_ur(i+1),
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q_a => q_dr(i),
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q_b => q_ur(i+1));
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sorter_ctrl_1 : sorter_ctrl
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generic map (
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NLEVELS => NLEVELS,
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NADDRBITS => i)
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port map (
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tm_din => q_u(i),
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tm_dout => data_u(i),
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tm_addr => addr_u(i),
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tm_we => we_u(i),
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lm_din => q_dl(i),
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lm_dout => data_dl(i),
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lm_addr => addr_dl(i),
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lm_we => we_dl(i),
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rm_din => q_dr(i),
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rm_dout => data_dr(i),
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rm_addr => addr_dr(i),
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rm_we => we_dr(i),
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up_in => up_update(i),
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up_in_val => up_update_path(i),
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up_in_addr => up_addr(i),
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up_out => low_update(i),
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up_out_val => low_update_path(i),
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up_out_addr => low_addr(i),
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low_in => low_update(i+1),
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low_in_val => low_update_path(i+1),
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low_in_addr => low_addr(i+1),
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low_out => up_update(i+1), -- connections to the next level
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low_out_val => up_update_path(i+1),
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low_out_addr => up_addr(i+1),
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clk => clk,
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clk_en => clk_en,
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ready_in => s_ready(i+1),
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ready_out => s_ready(i),
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rst_n => rst_n);
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end generate g1;
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-- top level
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-- On the top level we have only a single register
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process (clk, rst_n)
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variable rline : line;
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begin -- process
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if rst_n = '0' then -- asynchronous reset (active low)
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l0_reg <= DATA_REC_INIT_DATA;
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elsif clk'event and clk = '1' then -- rising clock edge
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dav <= '0';
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if we_u(0) = '1' then
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l0_reg <= data_u(0);
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dout <= data_u(0);
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dav <= '1';
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if SORT_DEBUG then
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write(rline, string'("OUT: "));
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write(rline, tdrec2stlv(data_u(0)));
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writeline(reports, rline);
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end if;
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elsif we = '1' then
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if SORT_DEBUG then
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write(rline, string'("IN: "));
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write(rline, tdrec2stlv(din));
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writeline(reports, rline);
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end if;
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l0_reg <= din;
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dout <= din;
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else
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dout <= l0_reg;
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end if;
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end if;
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end process;
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ready <= s_ready(0);
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q_ur(0) <= l0_reg;
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q_ul(0) <= l0_reg;
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up_update(0) <= we;
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up_update_path(0) <= din;
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up_addr(0) <= (others => '0');
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-- signals for the last level
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s_ready(NLEVELS) <= '1';
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--addr(NLEVELS) <= (others => '0');
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data_dr(NLEVELS) <= DATA_REC_INIT_DATA;
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data_dl(NLEVELS) <= DATA_REC_INIT_DATA;
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we_dl(NLEVELS) <= '0';
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we_dr(NLEVELS) <= '0';
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low_update(NLEVELS) <= '0';
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low_update_path(NLEVELS) <= DATA_REC_INIT_DATA;
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low_addr(0) <= (others => '0');
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end sorter_sys_arch1;
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