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[/] [hf-risc/] [trunk/] [hf-risc/] [platform/] [spartan3_starterkit/] [spartan3.vhd] - Blame information for rev 18

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hfrisc_soc is
        generic(
                address_width: integer := 14;
                memory_file : string := "code.txt";
                uart_support : string := "yes"
        );
        port (  clk_in:         in std_logic;
                reset_in:       in std_logic;
                int_in:         in std_logic;
                uart_read:      in std_logic;
                uart_write:     out std_logic
        );
end hfrisc_soc;
 
architecture top_level of hfrisc_soc is
        signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
        signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
        signal ext_irq: std_logic_vector(7 downto 0);
        signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
begin
        -- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
        process (reset_in, clk_in, clock)
        begin
                if reset_in = '1' then
                        clock <= '0';
                else
                        if clk_in'event and clk_in='1' then
                                clock <= not clock;
                        end if;
                end if;
        end process;
 
        -- reset synchronizer
        process (clock, reset_in)
        begin
                if (reset_in = '1') then
                        rff1 <= '1';
                        reset <= '1';
                elsif (clock'event and clock = '1') then
                        rff1 <= '0';
                        reset <= rff1;
                end if;
        end process;
 
 
        process (reset, clock, ext_irq, ram_enable_n)
        begin
                if reset = '1' then
                        ram_dly <= '0';
                        ext_irq <= x"00";
                elsif clock'event and clock = '1' then
                        ram_dly <= not ram_enable_n;
                        ext_irq <= "0000000" & int_in;
                end if;
        end process;
 
        stall <= '0';
        boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
        ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
        data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
        data_w_n_ram <= not data_we;
 
        -- HF-RISC core
        core: entity work.datapath
        port map(       clock => clock,
                        reset => reset,
                        stall => stall_cpu,
                        irq_vector => irq_vector_cpu,
                        irq => irq_cpu,
                        irq_ack => irq_ack_cpu,
                        address => address_cpu,
                        data_in => data_in_cpu,
                        data_out => data_out_cpu,
                        data_w => data_w_cpu,
                        data_access => data_access_cpu
        );
 
        -- peripherals / busmux logic
        peripherals_busmux: entity work.busmux
        generic map(
                uart_support => uart_support
        )
        port map(
                clock => clock,
                reset => reset,
 
                stall => stall,
 
                stall_cpu => stall_cpu,
                irq_vector_cpu => irq_vector_cpu,
                irq_cpu => irq_cpu,
                irq_ack_cpu => irq_ack_cpu,
                address_cpu => address_cpu,
                data_in_cpu => data_in_cpu,
                data_out_cpu => data_out_cpu,
                data_w_cpu => data_w_cpu,
                data_access_cpu => data_access_cpu,
 
                addr_mem => address,
                data_read_mem => data_read,
                data_write_mem => data_write,
                data_we_mem => data_we,
                extio_in => ext_irq,
                extio_out => open,
                uart_read => uart_read,
                uart_write => uart_write
        );
 
        -- instruction and data memory (boot RAM)
        boot_ram: entity work.ram
        generic map (memory_type => "DEFAULT")
        port map (
                clk                     => clock,
                enable                  => boot_enable,
                write_byte_enable       => "0000",
                address                 => address(31 downto 2),
                data_write              => (others => '0'),
                data_read               => data_read_boot
        );
 
        -- instruction and data memory (external RAM)
        memory0lb: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 0)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(0),
                data_i  => data_write(7 downto 0),
                data_o  => data_read_ram(7 downto 0)
        );
 
        memory0ub: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 1)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(1),
                data_i  => data_write(15 downto 8),
                data_o  => data_read_ram(15 downto 8)
        );
 
        memory1lb: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 2)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(2),
                data_i  => data_write(23 downto 16),
                data_o  => data_read_ram(23 downto 16)
        );
 
        memory1ub: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 3)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(3),
                data_i  => data_write(31 downto 24),
                data_o  => data_read_ram(31 downto 24)
        );
 
end top_level;
 

Line No.	Rev	Author	Line
1	13	serginhofr	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_unsigned.all;`
4
5	18	serginhofr	`entity hfrisc_soc is`
6	13	serginhofr	`generic(`
7			`address_width: integer := 14;`
8			`memory_file : string := "code.txt";`
9			`uart_support : string := "yes"`
10			`);`
11			`port ( clk_in: in std_logic;`
12			`reset_in: in std_logic;`
13			`int_in: in std_logic;`
14			`uart_read: in std_logic;`
15			`uart_write: out std_logic`
16			`);`
17	18	serginhofr	`end hfrisc_soc;`
18	13	serginhofr
19	18	serginhofr	`architecture top_level of hfrisc_soc is`
20			`signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;`
21			`signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);`
22	13	serginhofr	`signal ext_irq: std_logic_vector(7 downto 0);`
23			`signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);`
24			`begin`
25			`-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)`
26			`process (reset_in, clk_in, clock)`
27			`begin`
28			`if reset_in = '1' then`
29			`clock <= '0';`
30			`else`
31			`if clk_in'event and clk_in='1' then`
32			`clock <= not clock;`
33			`end if;`
34			`end if;`
35			`end process;`
36
37			`-- reset synchronizer`
38			`process (clock, reset_in)`
39			`begin`
40			`if (reset_in = '1') then`
41			`rff1 <= '1';`
42			`reset <= '1';`
43			`elsif (clock'event and clock = '1') then`
44			`rff1 <= '0';`
45			`reset <= rff1;`
46			`end if;`
47			`end process;`
48
49
50			`process (reset, clock, ext_irq, ram_enable_n)`
51			`begin`
52			`if reset = '1' then`
53			`ram_dly <= '0';`
54			`ext_irq <= x"00";`
55			`elsif clock'event and clock = '1' then`
56			`ram_dly <= not ram_enable_n;`
57			`ext_irq <= "0000000" & int_in;`
58			`end if;`
59			`end process;`
60
61			`stall <= '0';`
62			`boot_enable <= '1' when address(31 downto 28) = "0000" else '0';`
63			`ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';`
64			`data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;`
65			`data_w_n_ram <= not data_we;`
66
67			`-- HF-RISC core`
68			`core: entity work.datapath`
69			`port map( clock => clock,`
70			`reset => reset,`
71			`stall => stall_cpu,`
72			`irq_vector => irq_vector_cpu,`
73			`irq => irq_cpu,`
74			`irq_ack => irq_ack_cpu,`
75	18	serginhofr	`address => address_cpu,`
76	13	serginhofr	`data_in => data_in_cpu,`
77			`data_out => data_out_cpu,`
78			`data_w => data_w_cpu,`
79			`data_access => data_access_cpu`
80			`);`
81
82			`-- peripherals / busmux logic`
83			`peripherals_busmux: entity work.busmux`
84			`generic map(`
85			`uart_support => uart_support`
86			`)`
87			`port map(`
88			`clock => clock,`
89			`reset => reset,`
90
91			`stall => stall,`
92
93			`stall_cpu => stall_cpu,`
94			`irq_vector_cpu => irq_vector_cpu,`
95			`irq_cpu => irq_cpu,`
96			`irq_ack_cpu => irq_ack_cpu,`
97	18	serginhofr	`address_cpu => address_cpu,`
98	13	serginhofr	`data_in_cpu => data_in_cpu,`
99			`data_out_cpu => data_out_cpu,`
100			`data_w_cpu => data_w_cpu,`
101			`data_access_cpu => data_access_cpu,`
102
103			`addr_mem => address,`
104			`data_read_mem => data_read,`
105			`data_write_mem => data_write,`
106			`data_we_mem => data_we,`
107			`extio_in => ext_irq,`
108			`extio_out => open,`
109			`uart_read => uart_read,`
110			`uart_write => uart_write`
111			`);`
112
113			`-- instruction and data memory (boot RAM)`
114			`boot_ram: entity work.ram`
115			`generic map (memory_type => "DEFAULT")`
116			`port map (`
117			`clk => clock,`
118			`enable => boot_enable,`
119			`write_byte_enable => "0000",`
120			`address => address(31 downto 2),`
121			`data_write => (others => '0'),`
122			`data_read => data_read_boot`
123			`);`
124
125			`-- instruction and data memory (external RAM)`
126			`memory0lb: entity work.bram`
127			`generic map ( memory_file => memory_file,`
128			`data_width => 8,`
129			`address_width => address_width,`
130			`bank => 0)`
131			`port map(`
132			`clk => clock,`
133			`addr => address(address_width -1 downto 2),`
134			`cs_n => ram_enable_n,`
135			`we_n => data_w_n_ram(0),`
136			`data_i => data_write(7 downto 0),`
137			`data_o => data_read_ram(7 downto 0)`
138			`);`
139
140			`memory0ub: entity work.bram`
141			`generic map ( memory_file => memory_file,`
142			`data_width => 8,`
143			`address_width => address_width,`
144			`bank => 1)`
145			`port map(`
146			`clk => clock,`
147			`addr => address(address_width -1 downto 2),`
148			`cs_n => ram_enable_n,`
149			`we_n => data_w_n_ram(1),`
150			`data_i => data_write(15 downto 8),`
151			`data_o => data_read_ram(15 downto 8)`
152			`);`
153
154			`memory1lb: entity work.bram`
155			`generic map ( memory_file => memory_file,`
156			`data_width => 8,`
157			`address_width => address_width,`
158			`bank => 2)`
159			`port map(`
160			`clk => clock,`
161			`addr => address(address_width -1 downto 2),`
162			`cs_n => ram_enable_n,`
163			`we_n => data_w_n_ram(2),`
164			`data_i => data_write(23 downto 16),`
165			`data_o => data_read_ram(23 downto 16)`
166			`);`
167
168			`memory1ub: entity work.bram`
169			`generic map ( memory_file => memory_file,`
170			`data_width => 8,`
171			`address_width => address_width,`
172			`bank => 3)`
173			`port map(`
174			`clk => clock,`
175			`addr => address(address_width -1 downto 2),`
176			`cs_n => ram_enable_n,`
177			`we_n => data_w_n_ram(3),`
178			`data_i => data_write(31 downto 24),`
179			`data_o => data_read_ram(31 downto 24)`
180			`);`
181
182	18	serginhofr	`end top_level;`
183	13	serginhofr

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[/] [hf-risc/] [trunk/] [hf-risc/] [platform/] [spartan3_starterkit/] [spartan3.vhd] - Blame information for rev 18