1 |
13 |
serginhofr |
NET "clk_in" LOC = "T9";
|
2 |
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NET "clk_in" TNM_NET = "clk_in";
|
3 |
15 |
serginhofr |
TIMESPEC TS_clk_in = PERIOD "clk_in" 20 ns;
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4 |
13 |
serginhofr |
NET "int_in" LOC = "L13";
|
5 |
|
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NET "reset_in" LOC = "M13";
|
6 |
|
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NET "reset_in" CLOCK_DEDICATED_ROUTE = FALSE;
|
7 |
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|
8 |
|
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NET "uart_write" LOC = "R13"; #RX
|
9 |
|
|
NET "uart_read" LOC = "T13"; #TX
|
10 |
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|
|
11 |
18 |
serginhofr |
NET "extio_in<0>" LOC = "C5";
|
12 |
|
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NET "extio_in<1>" LOC = "C6";
|
13 |
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NET "extio_in<2>" LOC = "C7";
|
14 |
|
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NET "extio_in<3>" LOC = "C8";
|
15 |
|
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NET "extio_in<4>" LOC = "C9";
|
16 |
|
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NET "extio_in<5>" LOC = "A3";
|
17 |
|
|
NET "extio_in<6>" LOC = "A4";
|
18 |
|
|
NET "extio_in<7>" LOC = "A5";
|
19 |
|
|
|
20 |
|
|
NET "extio_out<0>" LOC = "D5";
|
21 |
|
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NET "extio_out<1>" LOC = "D6";
|
22 |
|
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NET "extio_out<2>" LOC = "E7";
|
23 |
|
|
NET "extio_out<3>" LOC = "D7";
|
24 |
|
|
NET "extio_out<4>" LOC = "D8";
|
25 |
|
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NET "extio_out<5>" LOC = "D10";
|
26 |
|
|
NET "extio_out<6>" LOC = "B4";
|
27 |
|
|
NET "extio_out<7>" LOC = "B5";
|
28 |
|
|
|
29 |
13 |
serginhofr |
NET "ram_address<2>" LOC = "L5";
|
30 |
|
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NET "ram_address<3>" LOC = "N3";
|
31 |
|
|
NET "ram_address<4>" LOC = "M4";
|
32 |
|
|
NET "ram_address<5>" LOC = "M3";
|
33 |
|
|
NET "ram_address<6>" LOC = "L4";
|
34 |
|
|
NET "ram_address<7>" LOC = "G4";
|
35 |
|
|
NET "ram_address<8>" LOC = "F3";
|
36 |
|
|
NET "ram_address<9>" LOC = "F4";
|
37 |
|
|
NET "ram_address<10>" LOC = "E3";
|
38 |
|
|
NET "ram_address<11>" LOC = "E4";
|
39 |
|
|
NET "ram_address<12>" LOC = "G5";
|
40 |
|
|
NET "ram_address<13>" LOC = "H3";
|
41 |
|
|
NET "ram_address<14>" LOC = "H4";
|
42 |
|
|
NET "ram_address<15>" LOC = "J4";
|
43 |
|
|
NET "ram_address<16>" LOC = "J3";
|
44 |
|
|
NET "ram_address<17>" LOC = "K3";
|
45 |
|
|
NET "ram_address<18>" LOC = "K5";
|
46 |
|
|
NET "ram_address<19>" LOC = "L3";
|
47 |
|
|
NET "ram_ce1_n" LOC = "P7";
|
48 |
|
|
NET "ram_ce2_n" LOC = "N5";
|
49 |
|
|
NET "ram_data<0>" LOC = "P2";
|
50 |
|
|
NET "ram_data<1>" LOC = "N2";
|
51 |
|
|
NET "ram_data<2>" LOC = "M2";
|
52 |
|
|
NET "ram_data<3>" LOC = "K1";
|
53 |
|
|
NET "ram_data<4>" LOC = "J1";
|
54 |
|
|
NET "ram_data<5>" LOC = "G2";
|
55 |
|
|
NET "ram_data<6>" LOC = "E1";
|
56 |
|
|
NET "ram_data<7>" LOC = "D1";
|
57 |
|
|
NET "ram_data<8>" LOC = "D2";
|
58 |
|
|
NET "ram_data<9>" LOC = "E2";
|
59 |
|
|
NET "ram_data<10>" LOC = "G1";
|
60 |
|
|
NET "ram_data<11>" LOC = "F5";
|
61 |
|
|
NET "ram_data<12>" LOC = "C3";
|
62 |
|
|
NET "ram_data<13>" LOC = "K2";
|
63 |
|
|
NET "ram_data<14>" LOC = "M1";
|
64 |
|
|
NET "ram_data<15>" LOC = "N1";
|
65 |
|
|
NET "ram_data<16>" LOC = "N7";
|
66 |
|
|
NET "ram_data<17>" LOC = "T8";
|
67 |
|
|
NET "ram_data<18>" LOC = "R6";
|
68 |
|
|
NET "ram_data<19>" LOC = "T5";
|
69 |
|
|
NET "ram_data<20>" LOC = "R5";
|
70 |
|
|
NET "ram_data<21>" LOC = "C2";
|
71 |
|
|
NET "ram_data<22>" LOC = "C1";
|
72 |
|
|
NET "ram_data<23>" LOC = "B1";
|
73 |
|
|
NET "ram_data<24>" LOC = "D3";
|
74 |
|
|
NET "ram_data<25>" LOC = "P8";
|
75 |
|
|
NET "ram_data<26>" LOC = "F2";
|
76 |
|
|
NET "ram_data<27>" LOC = "H1";
|
77 |
|
|
NET "ram_data<28>" LOC = "J2";
|
78 |
|
|
NET "ram_data<29>" LOC = "L2";
|
79 |
|
|
NET "ram_data<30>" LOC = "P1";
|
80 |
|
|
NET "ram_data<31>" LOC = "R1";
|
81 |
|
|
NET "ram_lb1_n" LOC = "P6";
|
82 |
|
|
NET "ram_lb2_n" LOC = "P5";
|
83 |
|
|
NET "ram_oe_n" LOC = "K4";
|
84 |
|
|
NET "ram_ub1_n" LOC = "T4";
|
85 |
|
|
NET "ram_ub2_n" LOC = "R4";
|
86 |
|
|
NET "ram_we_n" LOC = "G3";
|
87 |
|
|
|