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[/] [hf-risc/] [trunk/] [hf-risc/] [platform/] [spartan3e_nexys2/] [spartan3e_nexys2_xtea.vhd] - Blame information for rev 18

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hfrisc_soc is
        generic(
                address_width: integer := 14;
                memory_file : string := "code.txt";
                uart_support : string := "yes"
        );
        port (  clk_in:         in std_logic;
                reset_in:       in std_logic;
                int_in:         in std_logic;
                uart_read:      in std_logic;
                uart_write:     out std_logic
        );
end hfrisc_soc;
 
architecture top_level of hfrisc_soc is
        signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
        signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
        signal ext_irq: std_logic_vector(7 downto 0);
        signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
 
        signal ext_periph, ext_periph_dly, ready: std_logic;
        signal key: std_logic_vector(127 downto 0);
        signal input, output: std_logic_vector(63 downto 0);
        signal data_read_xtea: std_logic_vector(31 downto 0);
        signal control: std_logic_vector(1 downto 0);
begin
        -- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
        process (reset_in, clk_in, clock)
        begin
                if reset_in = '1' then
                        clock <= '0';
                else
                        if clk_in'event and clk_in='1' then
                                clock <= not clock;
                        end if;
                end if;
        end process;
 
        -- reset synchronizer
        process (clock, reset_in)
        begin
                if (reset_in = '1') then
                        rff1 <= '1';
                        reset <= '1';
                elsif (clock'event and clock = '1') then
                        rff1 <= '0';
                        reset <= rff1;
                end if;
        end process;
 
 
        process (reset, clock, ext_irq, ram_enable_n)
        begin
                if reset = '1' then
                        ram_dly <= '0';
                        ext_periph_dly <= '0';
                        ext_irq <= x"00";
                elsif clock'event and clock = '1' then
                        ram_dly <= not ram_enable_n;
                        ext_periph_dly <= ext_periph;
                        ext_irq <= "0000000" & int_in;
                end if;
        end process;
 
 
 
        process (clock, reset, address_cpu, key, input, output)
        begin
                if reset = '1' then
                        data_read_xtea <= (others => '0');
                elsif clock'event and clock = '1' then
                        if (ext_periph = '1') then      -- XTEA is at 0xfa000000
                                case address_cpu(7 downto 4) is
                                        when "0000" =>          -- control      0xfa000000      (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
                                                data_read_xtea <= x"000000" & "00000" & ready & control;
                                        when "0001" =>          -- key[0]       0xfa000010
                                                data_read_xtea <= key(127 downto 96);
                                        when "0010" =>          -- key[1]       0xfa000020
                                                data_read_xtea <= key(95 downto 64);
                                        when "0011" =>          -- key[2]       0xfa000030
                                                data_read_xtea <= key(63 downto 32);
                                        when "0100" =>          -- key[3]       0xfa000040
                                                data_read_xtea <= key(31 downto 0);
                                        when "0101" =>          -- input[0]     0xfa000050
                                                data_read_xtea <= input(63 downto 32);
                                        when "0110" =>          -- input[1]     0xfa000060
                                                data_read_xtea <= input(31 downto 0);
                                        when "0111" =>          -- output[0]    0xfa000070
                                                data_read_xtea <= output(63 downto 32);
                                        when "1000" =>          -- output[1]    0xfa000080
                                                data_read_xtea <= output(31 downto 0);
                                        when others =>
                                                data_read_xtea <= (others => '0');
                                end case;
                        end if;
                end if;
        end process;
 
        process (clock, reset, address_cpu, control, key, input, output)
        begin
                if reset = '1' then
                        key <= (others => '0');
                        input <= (others => '0');
                        control <= "00";
                elsif clock'event and clock = '1' then
                        if (ext_periph = '1' and data_we /= "0000") then        -- XTEA is at 0xfa000000
                                case address_cpu(7 downto 4) is
                                        when "0000" =>          -- control      0xfa000000      (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
                                                control <= data_write(1 downto 0);
                                        when "0001" =>          -- key[0]       0xfa000010
                                                key(127 downto 96) <= data_write;
                                        when "0010" =>          -- key[1]       0xfa000020
                                                key(95 downto 64) <= data_write;
                                        when "0011" =>          -- key[2]       0xfa000030
                                                key(63 downto 32) <= data_write;
                                        when "0100" =>          -- key[3]       0xfa000040
                                                key(31 downto 0) <= data_write;
                                        when "0101" =>          -- input[0]     0xfa000050
                                                input(63 downto 32) <= data_write;
                                        when "0110" =>          -- input[1]     0xfa000060
                                                input(31 downto 0) <= data_write;
                                        when others =>
                                end case;
                        end if;
                end if;
        end process;
 
        stall <= '0';
        boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
        ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
        ext_periph <= '1' when address(31 downto 24) = x"fa" else '0';
        data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
        data_w_n_ram <= not data_we;
 
        -- HF-RISC core
        core: entity work.datapath
        port map(       clock => clock,
                        reset => reset,
                        stall => stall_cpu,
                        irq_vector => irq_vector_cpu,
                        irq => irq_cpu,
                        irq_ack => irq_ack_cpu,
                        address => address_cpu,
                        data_in => data_in_cpu,
                        data_out => data_out_cpu,
                        data_w => data_w_cpu,
                        data_access => data_access_cpu
        );
 
        -- peripherals / busmux logic
        peripherals_busmux: entity work.busmux
        generic map(
                uart_support => uart_support
        )
        port map(
                clock => clock,
                reset => reset,
 
                stall => stall,
 
                stall_cpu => stall_cpu,
                irq_vector_cpu => irq_vector_cpu,
                irq_cpu => irq_cpu,
                irq_ack_cpu => irq_ack_cpu,
                address_cpu => address_cpu,
                data_in_cpu => data_in_cpu,
                data_out_cpu => data_out_cpu,
                data_w_cpu => data_w_cpu,
                data_access_cpu => data_access_cpu,
 
                addr_mem => address,
                data_read_mem => data_read,
                data_write_mem => data_write,
                data_we_mem => data_we,
                extio_in => ext_irq,
                extio_out => open,
                uart_read => uart_read,
                uart_write => uart_write
        );
 
        -- XTEA core
        crypto_core: entity work.xtea
        port map(       clock => clock,
                        reset => reset,
                        start => control(0),
                        encrypt => control(1),
                        key => key,
                        input => input,
                        output => output,
                        ready => ready
        );
 
        -- instruction and data memory (boot RAM)
        boot_ram: entity work.ram
        generic map (memory_type => "DEFAULT")
        port map (
                clk                     => clock,
                enable                  => boot_enable,
                write_byte_enable       => "0000",
                address                 => address(31 downto 2),
                data_write              => (others => '0'),
                data_read               => data_read_boot
        );
 
        -- instruction and data memory (external RAM)
        memory0lb: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 0)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(0),
                data_i  => data_write(7 downto 0),
                data_o  => data_read_ram(7 downto 0)
        );
 
        memory0ub: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 1)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(1),
                data_i  => data_write(15 downto 8),
                data_o  => data_read_ram(15 downto 8)
        );
 
        memory1lb: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 2)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(2),
                data_i  => data_write(23 downto 16),
                data_o  => data_read_ram(23 downto 16)
        );
 
        memory1ub: entity work.bram
        generic map (   memory_file => memory_file,
                                        data_width => 8,
                                        address_width => address_width,
                                        bank => 3)
        port map(
                clk     => clock,
                addr    => address(address_width -1 downto 2),
                cs_n    => ram_enable_n,
                we_n    => data_w_n_ram(3),
                data_i  => data_write(31 downto 24),
                data_o  => data_read_ram(31 downto 24)
        );
 
end top_level;
 

Line No.	Rev	Author	Line
1	13	serginhofr	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_unsigned.all;`
4
5	18	serginhofr	`entity hfrisc_soc is`
6	13	serginhofr	`generic(`
7			`address_width: integer := 14;`
8			`memory_file : string := "code.txt";`
9			`uart_support : string := "yes"`
10			`);`
11			`port ( clk_in: in std_logic;`
12			`reset_in: in std_logic;`
13			`int_in: in std_logic;`
14			`uart_read: in std_logic;`
15			`uart_write: out std_logic`
16			`);`
17	18	serginhofr	`end hfrisc_soc;`
18	13	serginhofr
19	18	serginhofr	`architecture top_level of hfrisc_soc is`
20	13	serginhofr	`signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;`
21	18	serginhofr	`signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);`
22	13	serginhofr	`signal ext_irq: std_logic_vector(7 downto 0);`
23			`signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);`
24
25			`signal ext_periph, ext_periph_dly, ready: std_logic;`
26			`signal key: std_logic_vector(127 downto 0);`
27			`signal input, output: std_logic_vector(63 downto 0);`
28			`signal data_read_xtea: std_logic_vector(31 downto 0);`
29			`signal control: std_logic_vector(1 downto 0);`
30			`begin`
31			`-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)`
32			`process (reset_in, clk_in, clock)`
33			`begin`
34			`if reset_in = '1' then`
35			`clock <= '0';`
36			`else`
37			`if clk_in'event and clk_in='1' then`
38			`clock <= not clock;`
39			`end if;`
40			`end if;`
41			`end process;`
42
43			`-- reset synchronizer`
44			`process (clock, reset_in)`
45			`begin`
46			`if (reset_in = '1') then`
47			`rff1 <= '1';`
48			`reset <= '1';`
49			`elsif (clock'event and clock = '1') then`
50			`rff1 <= '0';`
51			`reset <= rff1;`
52			`end if;`
53			`end process;`
54
55
56			`process (reset, clock, ext_irq, ram_enable_n)`
57			`begin`
58			`if reset = '1' then`
59			`ram_dly <= '0';`
60			`ext_periph_dly <= '0';`
61			`ext_irq <= x"00";`
62			`elsif clock'event and clock = '1' then`
63			`ram_dly <= not ram_enable_n;`
64			`ext_periph_dly <= ext_periph;`
65			`ext_irq <= "0000000" & int_in;`
66			`end if;`
67			`end process;`
68
69
70
71	18	serginhofr	`process (clock, reset, address_cpu, key, input, output)`
72	13	serginhofr	`begin`
73	18	serginhofr	`if reset = '1' then`
74			`data_read_xtea <= (others => '0');`
75			`elsif clock'event and clock = '1' then`
76			`if (ext_periph = '1') then -- XTEA is at 0xfa000000`
77			`case address_cpu(7 downto 4) is`
78			`when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)`
79			`data_read_xtea <= x"000000" & "00000" & ready & control;`
80			`when "0001" => -- key[0] 0xfa000010`
81			`data_read_xtea <= key(127 downto 96);`
82			`when "0010" => -- key[1] 0xfa000020`
83			`data_read_xtea <= key(95 downto 64);`
84			`when "0011" => -- key[2] 0xfa000030`
85			`data_read_xtea <= key(63 downto 32);`
86			`when "0100" => -- key[3] 0xfa000040`
87			`data_read_xtea <= key(31 downto 0);`
88			`when "0101" => -- input[0] 0xfa000050`
89			`data_read_xtea <= input(63 downto 32);`
90			`when "0110" => -- input[1] 0xfa000060`
91			`data_read_xtea <= input(31 downto 0);`
92			`when "0111" => -- output[0] 0xfa000070`
93			`data_read_xtea <= output(63 downto 32);`
94			`when "1000" => -- output[1] 0xfa000080`
95			`data_read_xtea <= output(31 downto 0);`
96			`when others =>`
97			`data_read_xtea <= (others => '0');`
98			`end case;`
99			`end if;`
100			`end if;`
101	13	serginhofr	`end process;`
102
103	18	serginhofr	`process (clock, reset, address_cpu, control, key, input, output)`
104	13	serginhofr	`begin`
105			`if reset = '1' then`
106			`key <= (others => '0');`
107			`input <= (others => '0');`
108			`control <= "00";`
109			`elsif clock'event and clock = '1' then`
110			`if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xfa000000`
111	18	serginhofr	`case address_cpu(7 downto 4) is`
112	13	serginhofr	`when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)`
113			`control <= data_write(1 downto 0);`
114			`when "0001" => -- key[0] 0xfa000010`
115			`key(127 downto 96) <= data_write;`
116			`when "0010" => -- key[1] 0xfa000020`
117			`key(95 downto 64) <= data_write;`
118			`when "0011" => -- key[2] 0xfa000030`
119			`key(63 downto 32) <= data_write;`
120			`when "0100" => -- key[3] 0xfa000040`
121			`key(31 downto 0) <= data_write;`
122			`when "0101" => -- input[0] 0xfa000050`
123			`input(63 downto 32) <= data_write;`
124			`when "0110" => -- input[1] 0xfa000060`
125			`input(31 downto 0) <= data_write;`
126			`when others =>`
127			`end case;`
128			`end if;`
129			`end if;`
130			`end process;`
131
132			`stall <= '0';`
133			`boot_enable <= '1' when address(31 downto 28) = "0000" else '0';`
134			`ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';`
135			`ext_periph <= '1' when address(31 downto 24) = x"fa" else '0';`
136			`data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;`
137			`data_w_n_ram <= not data_we;`
138
139			`-- HF-RISC core`
140			`core: entity work.datapath`
141			`port map( clock => clock,`
142			`reset => reset,`
143			`stall => stall_cpu,`
144			`irq_vector => irq_vector_cpu,`
145			`irq => irq_cpu,`
146			`irq_ack => irq_ack_cpu,`
147	18	serginhofr	`address => address_cpu,`
148	13	serginhofr	`data_in => data_in_cpu,`
149			`data_out => data_out_cpu,`
150			`data_w => data_w_cpu,`
151			`data_access => data_access_cpu`
152			`);`
153
154			`-- peripherals / busmux logic`
155			`peripherals_busmux: entity work.busmux`
156			`generic map(`
157			`uart_support => uart_support`
158			`)`
159			`port map(`
160			`clock => clock,`
161			`reset => reset,`
162
163			`stall => stall,`
164
165			`stall_cpu => stall_cpu,`
166			`irq_vector_cpu => irq_vector_cpu,`
167			`irq_cpu => irq_cpu,`
168			`irq_ack_cpu => irq_ack_cpu,`
169	18	serginhofr	`address_cpu => address_cpu,`
170	13	serginhofr	`data_in_cpu => data_in_cpu,`
171			`data_out_cpu => data_out_cpu,`
172			`data_w_cpu => data_w_cpu,`
173			`data_access_cpu => data_access_cpu,`
174
175			`addr_mem => address,`
176			`data_read_mem => data_read,`
177			`data_write_mem => data_write,`
178			`data_we_mem => data_we,`
179			`extio_in => ext_irq,`
180			`extio_out => open,`
181			`uart_read => uart_read,`
182			`uart_write => uart_write`
183			`);`
184
185			`-- XTEA core`
186			`crypto_core: entity work.xtea`
187			`port map( clock => clock,`
188			`reset => reset,`
189			`start => control(0),`
190			`encrypt => control(1),`
191			`key => key,`
192			`input => input,`
193			`output => output,`
194			`ready => ready`
195			`);`
196
197			`-- instruction and data memory (boot RAM)`
198			`boot_ram: entity work.ram`
199			`generic map (memory_type => "DEFAULT")`
200			`port map (`
201			`clk => clock,`
202			`enable => boot_enable,`
203			`write_byte_enable => "0000",`
204			`address => address(31 downto 2),`
205			`data_write => (others => '0'),`
206			`data_read => data_read_boot`
207			`);`
208
209			`-- instruction and data memory (external RAM)`
210			`memory0lb: entity work.bram`
211			`generic map ( memory_file => memory_file,`
212			`data_width => 8,`
213			`address_width => address_width,`
214			`bank => 0)`
215			`port map(`
216			`clk => clock,`
217			`addr => address(address_width -1 downto 2),`
218			`cs_n => ram_enable_n,`
219			`we_n => data_w_n_ram(0),`
220			`data_i => data_write(7 downto 0),`
221			`data_o => data_read_ram(7 downto 0)`
222			`);`
223
224			`memory0ub: entity work.bram`
225			`generic map ( memory_file => memory_file,`
226			`data_width => 8,`
227			`address_width => address_width,`
228			`bank => 1)`
229			`port map(`
230			`clk => clock,`
231			`addr => address(address_width -1 downto 2),`
232			`cs_n => ram_enable_n,`
233			`we_n => data_w_n_ram(1),`
234			`data_i => data_write(15 downto 8),`
235			`data_o => data_read_ram(15 downto 8)`
236			`);`
237
238			`memory1lb: entity work.bram`
239			`generic map ( memory_file => memory_file,`
240			`data_width => 8,`
241			`address_width => address_width,`
242			`bank => 2)`
243			`port map(`
244			`clk => clock,`
245			`addr => address(address_width -1 downto 2),`
246			`cs_n => ram_enable_n,`
247			`we_n => data_w_n_ram(2),`
248			`data_i => data_write(23 downto 16),`
249			`data_o => data_read_ram(23 downto 16)`
250			`);`
251
252			`memory1ub: entity work.bram`
253			`generic map ( memory_file => memory_file,`
254			`data_width => 8,`
255			`address_width => address_width,`
256			`bank => 3)`
257			`port map(`
258			`clk => clock,`
259			`addr => address(address_width -1 downto 2),`
260			`cs_n => ram_enable_n,`
261			`we_n => data_w_n_ram(3),`
262			`data_i => data_write(31 downto 24),`
263			`data_o => data_read_ram(31 downto 24)`
264			`);`
265
266	18	serginhofr	`end top_level;`
267	13	serginhofr

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[/] [hf-risc/] [trunk/] [hf-risc/] [platform/] [spartan3e_nexys2/] [spartan3e_nexys2_xtea.vhd] - Blame information for rev 18