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[/] [hf-risc/] [trunk/] [hf-risc/] [sim/] [ram.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 13 serginhofr
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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entity bram is
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        generic(memory_file : string := "code.txt";
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                data_width: integer := 8;                       -- data width (fixed)
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                address_width: integer := 16;                   -- address width
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                bank: integer := 0);                                     -- memory bank (0,1,2,3)
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        port(
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        clk : in std_logic;                                     --clock
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        addr : in std_logic_vector(address_width - 1 downto 2);         --address bus
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        cs_n : in std_logic;                                    --chip select
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        we_n : in std_logic;                                    --write enable
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        data_i: in std_logic_vector(data_width - 1 downto 0);    --write data bus
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        data_o: out std_logic_vector(data_width - 1 downto 0)    --read data bus
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        );
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end bram;
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architecture memory of bram is
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type ram is array(2 ** address_width -1 downto 0) of std_logic_vector(data_width - 1 downto 0);
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signal ram1 : ram := (others => (others => '0'));
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begin
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        process(clk)
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                variable data : std_logic_vector(data_width*4 -1 downto 0);
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                variable index : natural := 0;
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                file load_file : text open read_mode is "code.txt";
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                variable hex_file_line : line;
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        begin
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                --Load in the ram executable image
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                if index = 0 then
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                        while not endfile(load_file) loop
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                                readline(load_file, hex_file_line);
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                                hread(hex_file_line, data);
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                                ram1(conv_integer(index)) <= data(((bank+1)*data_width)-1 downto bank*data_width);
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                                index := index + 1;
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                        end loop;
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                end if;
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                if (clk'event and clk = '1') then
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                        if(cs_n = '0') then
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                                if(we_n = '0') then
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                                        ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
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                                else
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                                        data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
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                                end if;
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                        end if;
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                end if;
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        end process;
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end memory;
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