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serginhofr |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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entity uart is
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generic(log_file : string := "UNUSED");
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port( clk : in std_logic;
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reset : in std_logic;
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divisor : in std_logic_vector(11 downto 0);
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enable_read : in std_logic;
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enable_write : in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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uart_read : in std_logic;
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uart_write : out std_logic;
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busy_write : out std_logic;
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data_avail : out std_logic
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);
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end;
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architecture logic of uart is
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signal delay_write_reg : std_logic_vector(11 downto 0);
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signal bits_write_reg : std_logic_vector(3 downto 0);
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signal data_write_reg : std_logic_vector(8 downto 0);
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signal delay_read_reg : std_logic_vector(11 downto 0);
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signal bits_read_reg : std_logic_vector(3 downto 0);
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signal data_read_reg : std_logic_vector(7 downto 0);
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signal data_save_reg : std_logic_vector(8 downto 0);
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signal busy_write_sig : std_logic;
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signal read_value_reg : std_logic_vector(7 downto 0);
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signal uart_read2 : std_logic;
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begin
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uart_proc:
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process(clk, reset, enable_read, enable_write, data_in, data_write_reg, bits_write_reg,
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delay_write_reg, data_read_reg, bits_read_reg, delay_read_reg, data_save_reg,
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read_value_reg, uart_read2, busy_write_sig, uart_read)
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begin
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uart_read2 <= read_value_reg(read_value_reg'length - 1);
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if reset = '1' then
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data_write_reg <= x"00" & '1';
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bits_write_reg <= "0000";
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delay_write_reg <= (others => '0');
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read_value_reg <= (others => '1');
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data_read_reg <= (others => '0');
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bits_read_reg <= "0000";
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delay_read_reg <= (others => '0');
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data_save_reg <= (others => '0');
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elsif clk'event and clk = '1' then
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-- UART write
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if bits_write_reg = "0000" then --nothing left to write?
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if enable_write = '1' then
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delay_write_reg <= (others => '0'); --delay before next bit
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bits_write_reg <= "1010"; --number of bits to write
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data_write_reg <= data_in & '0'; --remember data & start bit
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end if;
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else
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if delay_write_reg /= divisor then
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delay_write_reg <= delay_write_reg + 1; --delay before next bit
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else
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delay_write_reg <= (others => '0'); --reset delay
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bits_write_reg <= bits_write_reg - 1; --bits left to write
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data_write_reg <= '1' & data_write_reg(8 downto 1);
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end if;
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end if;
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-- average uart_read signal
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if uart_read = '1' then
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if read_value_reg /= x"ff" then
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read_value_reg <= read_value_reg + 1;
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end if;
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else
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if read_value_reg /= x"00" then
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read_value_reg <= read_value_reg - 1;
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end if;
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end if;
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-- UART read
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if delay_read_reg = x"0000" then --done delay for read?
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if bits_read_reg = "0000" then --nothing left to read?
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if uart_read2 = '0' then --wait for start bit
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delay_read_reg <= '0' & divisor(11 downto 1); --half period
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bits_read_reg <= "1001"; --bits left to read
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end if;
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else
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delay_read_reg <= divisor; --initialize delay
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bits_read_reg <= bits_read_reg - 1; --bits left to read
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data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
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end if;
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else
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delay_read_reg <= delay_read_reg - 1; --delay
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end if;
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if bits_read_reg = "0000" and delay_read_reg = divisor then
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data_save_reg <= '1' & data_read_reg;
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elsif enable_read = '1' then
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data_save_reg(8) <= '0'; --data_available
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end if;
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end if;
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if bits_write_reg /= "0000"
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-- and log_file = "UNUSED"
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then
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busy_write_sig <= '1';
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else
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busy_write_sig <= '0';
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end if;
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uart_write <= data_write_reg(0);
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busy_write <= busy_write_sig;
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data_avail <= data_save_reg(8);
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data_out <= data_save_reg(7 downto 0);
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end process;
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-- synthesis_off
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uart_logger:
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if log_file /= "UNUSED" generate
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uart_proc:
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process(clk, enable_write, data_in)
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file store_file : text open write_mode is log_file;
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variable hex_file_line : line;
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variable c : character;
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variable index : natural;
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variable line_length : natural := 0;
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begin
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if clk'event and clk = '1' and busy_write_sig = '0' then
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if enable_write = '1' then
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index := conv_integer(data_in(6 downto 0));
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if index /= 10 then
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c := character'val(index);
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write(hex_file_line, c);
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line_length := line_length + 1;
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end if;
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if index = 10 or line_length >= 72 then
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writeline(store_file, hex_file_line);
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line_length := 0;
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end if;
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end if;
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end if;
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end process;
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end generate;
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-- synthesis_on
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end;
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