URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

Subversion Repositories hf-risc

[/] [hf-risc/] [trunk/] [hf-riscv/] [core_rv32i/] [datapath.vhd] - Blame information for rev 19

Go to most recent revision | Details | Compare with Previous | View Log


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
entity datapath is
        port (  clock:          in std_logic;
                reset:          in std_logic;
 
                stall:          in std_logic;
 
                irq_vector:     in std_logic_vector(31 downto 0);
                irq:            in std_logic;
                irq_ack:        out std_logic;
                exception:      out std_logic;
 
                address:        out std_logic_vector(31 downto 0);
                data_in:        in std_logic_vector(31 downto 0);
                data_out:       out std_logic_vector(31 downto 0);
                data_w:         out std_logic_vector(3 downto 0);
                data_access:    out std_logic
        );
end datapath;
 
architecture arch_datapath of datapath is
-- datapath signals
        signal inst_in_s, data_in_s, pc, pc_last, pc_last2, pc_plus4, pc_next, result, branch, ext32b, ext32h, alu_src1, alu_src2: std_logic_vector(31 downto 0);
        signal ext32: std_logic_vector(31 downto 12);
        signal opcode, funct7: std_logic_vector(6 downto 0);
        signal funct3: std_logic_vector(2 downto 0);
        signal read_reg1, read_reg2, write_reg, rs1, rs2, rd: std_logic_vector(4 downto 0);
        signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
        signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
        signal imm_u: std_logic_vector(31 downto 12);
        signal wreg, zero, less_than, branch_taken, jump_taken, mwait, stall_reg: std_logic;
        signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
 
-- control signals
        signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
        signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
        signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0);
        signal alu_op_ctl: std_logic_vector(3 downto 0);
 
        signal rs1_r, rs2_r, rd_r: std_logic_vector(4 downto 0);
        signal imm_i_r, imm_s_r, imm_sb_r, imm_uj_r: std_logic_vector(31 downto 0);
        signal imm_u_r: std_logic_vector(31 downto 12);
        signal reg_write_ctl_r, alu_src1_ctl_r, sig_read_ctl_r, reg_to_mem_r, mem_to_reg_r, mem_to_reg_r_dly: std_logic;
        signal jump_ctl_r, mem_write_ctl_r, mem_read_ctl_r: std_logic_vector(1 downto 0);
        signal alu_src2_ctl_r, branch_ctl_r: std_logic_vector(2 downto 0);
        signal alu_op_ctl_r: std_logic_vector(3 downto 0);
begin
 
--
-- FETCH STAGE
--
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
 
        -- program counter logic
        process(clock, reset, reg_to_mem_r, mem_to_reg_r, mwait, stall)
        begin
                if reset = '1' then
                        pc <= (others => '0');
                        pc_last <= (others => '0');
                        pc_last2 <= (others => '0');
                elsif clock'event and clock = '1' then
                        if stall = '0' then
                                if mwait = '0' then
                                        pc <= pc_next;
                                        pc_last <= pc;
                                        pc_last2 <= pc_last;
                                else
                                        if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1') and bds = '0' then
                                                pc <= pc_last;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        pc_plus4 <=     pc + 4;
 
        pc_next <=      irq_vector when (irq = '1' and irq_ack_s = '1') or except = '1' else
                        branch when branch_taken = '1' or jump_taken = '1' else
                        pc_plus4;
 
        -- interrupt acknowledge logic
        irq_ack_s <= '1' when irq = '1' and
                bds = '0' and branch_taken = '0' and jump_taken = '0' and
                reg_to_mem_r = '0' and mem_to_reg_r = '0' else '0';
 
        irq_ack <= irq_ack_s_dly;
 
        exception <= '1' when except = '1' else '0';
 
        process(clock, reset, irq, irq_ack_s, mem_to_reg_r, mwait, stall)
        begin
                if reset = '1' then
                        irq_ack_s_dly <= '0';
                        bds <= '0';
                        mem_to_reg_r_dly <= '0';
                        stall_reg <= '0';
                        data_access_s_dly <= '0';
                elsif clock'event and clock = '1' then
                        stall_reg <= stall;
                        if stall = '0' then
                                mem_to_reg_r_dly <= mem_to_reg_r;
                                data_access_s_dly <= data_access_s;
                                if mwait = '0' then
                                        irq_ack_s_dly <= irq_ack_s;
                                        if branch_taken = '1' or jump_taken = '1' then
                                                bds <= '1';
                                        else
                                                bds <= '0';
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
--
-- DECODE STAGE
--
-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches
 
        -- instruction decode
        inst_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);
 
        opcode <= inst_in_s(6 downto 0);
        funct3 <= inst_in_s(14 downto 12);
        funct7 <= inst_in_s(31 downto 25);
        rd <= inst_in_s(11 downto 7);
        rs1 <= inst_in_s(19 downto 15);
        rs2 <= inst_in_s(24 downto 20);
        imm_i <= ext32(31 downto 12) & inst_in_s(31 downto 20);
        imm_s <= ext32(31 downto 12) & inst_in_s(31 downto 25) & inst_in_s(11 downto 7);
        imm_sb <= ext32(31 downto 13) & inst_in_s(31) & inst_in_s(7) & inst_in_s(30 downto 25) & inst_in_s(11 downto 8) & '0';
        imm_u <= inst_in_s(31 downto 12);
        imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0';
        ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0');
 
        -- control unit
        control_unit: entity work.control
        port map(       opcode => opcode,
                        funct3 => funct3,
                        funct7 => funct7,
                        reg_write => reg_write_ctl,
                        alu_src1 => alu_src1_ctl,
                        alu_src2 => alu_src2_ctl,
                        alu_op => alu_op_ctl,
                        jump => jump_ctl,
                        branch => branch_ctl,
                        mem_write => mem_write_ctl,
                        mem_read => mem_read_ctl,
                        sig_read => sig_read_ctl
        );
 
        reg_to_mem <= '1' when mem_write_ctl /= "00" else '0';
        mem_to_reg <= '1' when mem_read_ctl /= "00" else '0';
 
        process(clock, reset, irq_ack_s, bds, mwait, stall)
        begin
                if reset = '1' then
                        rd_r <= (others => '0');
                        rs1_r <= (others => '0');
                        rs2_r <= (others => '0');
                        imm_i_r <= (others => '0');
                        imm_s_r <= (others => '0');
                        imm_sb_r <= (others => '0');
                        imm_u_r <= (others => '0');
                        imm_uj_r <= (others => '0');
                        reg_write_ctl_r <= '0';
                        alu_src1_ctl_r <= '0';
                        alu_src2_ctl_r <= (others => '0');
                        alu_op_ctl_r <= (others => '0');
                        jump_ctl_r <= (others => '0');
                        branch_ctl_r <= (others => '0');
                        mem_write_ctl_r <= (others => '0');
                        mem_read_ctl_r <= (others => '0');
                        sig_read_ctl_r <= '0';
                        reg_to_mem_r <= '0';
                        mem_to_reg_r <= '0';
                elsif clock'event and clock = '1' then
                        if stall = '0' then
                                if irq_ack_s = '1' then
                                        rd_r <= (others => '0');
                                        rs1_r <= (others => '0');
                                        rs2_r <= (others => '0');
                                        imm_i_r <= (others => '0');
                                        imm_s_r <= (others => '0');
                                        imm_sb_r <= (others => '0');
                                        imm_u_r <= (others => '0');
                                        imm_uj_r <= (others => '0');
                                        reg_write_ctl_r <= '0';
                                        alu_src1_ctl_r <= '0';
                                        alu_src2_ctl_r <= (others => '0');
                                        alu_op_ctl_r <= (others => '0');
                                        jump_ctl_r <= (others => '0');
                                        branch_ctl_r <= (others => '0');
                                        mem_write_ctl_r <= (others => '0');
                                        mem_read_ctl_r <= (others => '0');
                                        sig_read_ctl_r <= '0';
                                        reg_to_mem_r <= '0';
                                        mem_to_reg_r <= '0';
                                else
                                        if mwait = '0' then
                                                if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1' or branch_taken = '1' or jump_taken = '1' or bds = '1') then
                                                        rd_r <= (others => '0');
                                                        rs1_r <= (others => '0');
                                                        rs2_r <= (others => '0');
                                                        imm_i_r <= (others => '0');
                                                        imm_s_r <= (others => '0');
                                                        imm_sb_r <= (others => '0');
                                                        imm_u_r <= (others => '0');
                                                        imm_uj_r <= (others => '0');
                                                        reg_write_ctl_r <= '0';
                                                        alu_src1_ctl_r <= '0';
                                                        alu_src2_ctl_r <= (others => '0');
                                                        alu_op_ctl_r <= (others => '0');
                                                        jump_ctl_r <= (others => '0');
                                                        branch_ctl_r <= (others => '0');
                                                        mem_write_ctl_r <= (others => '0');
                                                        mem_read_ctl_r <= (others => '0');
                                                        sig_read_ctl_r <= '0';
                                                        reg_to_mem_r <= '0';
                                                        mem_to_reg_r <= '0';
                                                else
                                                        rd_r <= rd;
                                                        rs1_r <= rs1;
                                                        rs2_r <= rs2;
                                                        imm_i_r <= imm_i;
                                                        imm_s_r <= imm_s;
                                                        imm_sb_r <= imm_sb;
                                                        imm_u_r <= imm_u;
                                                        imm_uj_r <= imm_uj;
                                                        reg_write_ctl_r <= reg_write_ctl;
                                                        alu_src1_ctl_r <= alu_src1_ctl;
                                                        alu_src2_ctl_r <= alu_src2_ctl;
                                                        alu_op_ctl_r <= alu_op_ctl;
                                                        jump_ctl_r <= jump_ctl;
                                                        branch_ctl_r <= branch_ctl;
                                                        mem_write_ctl_r <= mem_write_ctl;
                                                        mem_read_ctl_r <= mem_read_ctl;
                                                        sig_read_ctl_r <= sig_read_ctl;
                                                        reg_to_mem_r <= reg_to_mem;
                                                        mem_to_reg_r <= mem_to_reg;
                                                end if;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
--
-- EXECUTE STAGE
--
 
-- 3rd stage (a) register file access (read)
        -- the register file
        register_bank: entity work.reg_bank
        port map(       clock => clock,
                        read_reg1 => read_reg1,
                        read_reg2 => read_reg2,
                        write_reg => write_reg,
                        wreg => wreg,
                        write_data => write_data,
                        read_data1 => read_data1,
                        read_data2 => read_data2
        );
 
        -- register file read/write selection and write enable
        read_reg1 <= rs1_r;
        read_reg2 <= rs2_r;
        write_reg <= rd_r;
        wreg <= (reg_write_ctl_r or mem_to_reg_r_dly) and not mwait and not stall_reg;
 
-- 3rd stage (b) ALU operation
        alu: entity work.alu
        port map(       op1 => alu_src1,
                        op2 => alu_src2,
                        alu_op => alu_op_ctl_r,
                        result => result,
                        zero => zero,
                        less_than => less_than
        );
 
        alu_src1 <= read_data1 when alu_src1_ctl_r = '0' else pc_last2;
        alu_src2 <=     imm_u_r & x"000" when alu_src2_ctl_r = "000" else
                        imm_i_r when alu_src2_ctl_r = "001" else
                        imm_s_r when alu_src2_ctl_r = "010" else
                        pc when alu_src2_ctl_r = "011" else
                        x"000000" & "000" & rs2_r when alu_src2_ctl_r = "100" else
                        read_data2;
 
        branch_src1 <= read_data1 when jump_ctl_r = "11" else pc_last2;
        branch_src2 <= imm_uj_r when jump_ctl_r = "10" else
                        imm_i_r when jump_ctl_r = "11" else imm_sb_r;
 
        branch <= branch_src1 + branch_src2;
 
        branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or                                               -- BEQ
                                (zero = '0' and branch_ctl_r = "010") or                                         -- BNE
                                (less_than = '1' and branch_ctl_r = "011") or                                           -- BLT
                                (less_than = '0' and branch_ctl_r = "100") or                                            -- BGE
                                (less_than = '1' and branch_ctl_r = "101") or                                           -- BLTU
                                (less_than = '0' and branch_ctl_r = "110")                                               -- BGEU
                                else '0';
        except <= '1' when branch_ctl_r = "111" else '0';
        jump_taken <= '1' when jump_ctl_r /= "00" else '0';
 
        address <= result when data_access_s = '1' and mwait = '1' else pc;
        data_access_s <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0';
        mwait <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
        data_access <= mwait;
 
 
-- 3rd stage (c) data memory / write back operation, register file access (write)
        -- memory access, store operations
        process(mem_write_ctl_r, result, read_data2)
        begin
                case mem_write_ctl_r is
                        when "11" =>                    -- store word
                                data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
                                data_w <= "1111";
                        when "01" =>                    -- store byte
                                data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
                                case result(1 downto 0) is
                                        when "11" => data_w <= "0001";
                                        when "10" => data_w <= "0010";
                                        when "01" => data_w <= "0100";
                                        when others => data_w <= "1000";
                                end case;
                        when "10" =>                    -- store half word
                                data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(7 downto 0) & read_data2(15 downto 8);
                                case result(1) is
                                        when '1' => data_w <= "0011";
                                        when others => data_w <= "1100";
                                end case;
                        when others =>                  -- WTF??
                                data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
                                data_w <= "0000";
                end case;
        end process;
 
        -- memory access, load operations
        process(mem_read_ctl_r, result, data_in)
        begin
                case mem_read_ctl_r is
                        when "01" =>                    -- load byte
                                case result(1 downto 0) is
                                        when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
                                        when "10" => data_in_s <= x"000000" & data_in(15 downto 8);
                                        when "01" => data_in_s <= x"000000" & data_in(23 downto 16);
                                        when others => data_in_s <= x"000000" & data_in(31 downto 24);
 
                                end case;
                        when "10" =>                    -- load half word
                                case result(1) is
                                        when '1' => data_in_s <= x"0000" & data_in(7 downto 0) & data_in(15 downto 8);
                                        when others => data_in_s <= x"0000" & data_in(23 downto 16) & data_in(31 downto 24);
                                end case;
                        when others =>                  -- load word
                                data_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);
                end case;
        end process;
 
        -- write back
        ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or sig_read_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
        ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or sig_read_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
 
        write_data <= data_in_s when mem_read_ctl_r = "11" else
                        ext32b when mem_read_ctl_r = "01" else
                        ext32h when mem_read_ctl_r = "10" else
                        pc_last when jump_taken = '1' else result;
 
end arch_datapath;
 

Line No.	Rev	Author	Line
1	13	serginhofr	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_unsigned.all;`
4			`use ieee.std_logic_arith.all;`
5
6			`entity datapath is`
7			`port ( clock: in std_logic;`
8			`reset: in std_logic;`
9
10			`stall: in std_logic;`
11
12			`irq_vector: in std_logic_vector(31 downto 0);`
13			`irq: in std_logic;`
14			`irq_ack: out std_logic;`
15			`exception: out std_logic;`
16
17	18	serginhofr	`address: out std_logic_vector(31 downto 0);`
18	13	serginhofr	`data_in: in std_logic_vector(31 downto 0);`
19			`data_out: out std_logic_vector(31 downto 0);`
20			`data_w: out std_logic_vector(3 downto 0);`
21			`data_access: out std_logic`
22			`);`
23			`end datapath;`
24
25			`architecture arch_datapath of datapath is`
26			`-- datapath signals`
27			`signal inst_in_s, data_in_s, pc, pc_last, pc_last2, pc_plus4, pc_next, result, branch, ext32b, ext32h, alu_src1, alu_src2: std_logic_vector(31 downto 0);`
28			`signal ext32: std_logic_vector(31 downto 12);`
29			`signal opcode, funct7: std_logic_vector(6 downto 0);`
30			`signal funct3: std_logic_vector(2 downto 0);`
31			`signal read_reg1, read_reg2, write_reg, rs1, rs2, rd: std_logic_vector(4 downto 0);`
32			`signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);`
33			`signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);`
34			`signal imm_u: std_logic_vector(31 downto 12);`
35	18	serginhofr	`signal wreg, zero, less_than, branch_taken, jump_taken, mwait, stall_reg: std_logic;`
36			`signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;`
37	13	serginhofr
38			`-- control signals`
39			`signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;`
40			`signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);`
41			`signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0);`
42			`signal alu_op_ctl: std_logic_vector(3 downto 0);`
43
44			`signal rs1_r, rs2_r, rd_r: std_logic_vector(4 downto 0);`
45			`signal imm_i_r, imm_s_r, imm_sb_r, imm_uj_r: std_logic_vector(31 downto 0);`
46			`signal imm_u_r: std_logic_vector(31 downto 12);`
47			`signal reg_write_ctl_r, alu_src1_ctl_r, sig_read_ctl_r, reg_to_mem_r, mem_to_reg_r, mem_to_reg_r_dly: std_logic;`
48			`signal jump_ctl_r, mem_write_ctl_r, mem_read_ctl_r: std_logic_vector(1 downto 0);`
49			`signal alu_src2_ctl_r, branch_ctl_r: std_logic_vector(2 downto 0);`
50			`signal alu_op_ctl_r: std_logic_vector(3 downto 0);`
51			`begin`
52
53			`--`
54			`-- FETCH STAGE`
55			`--`
56			`-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic`
57
58			`-- program counter logic`
59	18	serginhofr	`process(clock, reset, reg_to_mem_r, mem_to_reg_r, mwait, stall)`
60	13	serginhofr	`begin`
61			`if reset = '1' then`
62			`pc <= (others => '0');`
63			`pc_last <= (others => '0');`
64			`pc_last2 <= (others => '0');`
65			`elsif clock'event and clock = '1' then`
66			`if stall = '0' then`
67	18	serginhofr	`if mwait = '0' then`
68	13	serginhofr	`pc <= pc_next;`
69			`pc_last <= pc;`
70			`pc_last2 <= pc_last;`
71			`else`
72	17	serginhofr	`if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1') and bds = '0' then`
73	13	serginhofr	`pc <= pc_last;`
74			`end if;`
75			`end if;`
76			`end if;`
77			`end if;`
78			`end process;`
79
80			`pc_plus4 <= pc + 4;`
81
82			`pc_next <= irq_vector when (irq = '1' and irq_ack_s = '1') or except = '1' else`
83			`branch when branch_taken = '1' or jump_taken = '1' else`
84			`pc_plus4;`
85
86			`-- interrupt acknowledge logic`
87			`irq_ack_s <= '1' when irq = '1' and`
88			`bds = '0' and branch_taken = '0' and jump_taken = '0' and`
89			`reg_to_mem_r = '0' and mem_to_reg_r = '0' else '0';`
90
91			`irq_ack <= irq_ack_s_dly;`
92
93			`exception <= '1' when except = '1' else '0';`
94
95	18	serginhofr	`process(clock, reset, irq, irq_ack_s, mem_to_reg_r, mwait, stall)`
96	13	serginhofr	`begin`
97			`if reset = '1' then`
98			`irq_ack_s_dly <= '0';`
99			`bds <= '0';`
100			`mem_to_reg_r_dly <= '0';`
101			`stall_reg <= '0';`
102	18	serginhofr	`data_access_s_dly <= '0';`
103	13	serginhofr	`elsif clock'event and clock = '1' then`
104			`stall_reg <= stall;`
105			`if stall = '0' then`
106			`mem_to_reg_r_dly <= mem_to_reg_r;`
107	18	serginhofr	`data_access_s_dly <= data_access_s;`
108			`if mwait = '0' then`
109	13	serginhofr	`irq_ack_s_dly <= irq_ack_s;`
110			`if branch_taken = '1' or jump_taken = '1' then`
111			`bds <= '1';`
112			`else`
113			`bds <= '0';`
114			`end if;`
115			`end if;`
116			`end if;`
117			`end if;`
118			`end process;`
119
120			`--`
121			`-- DECODE STAGE`
122			`--`
123			`-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches`
124
125			`-- instruction decode`
126	18	serginhofr	`inst_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);`
127	13	serginhofr
128			`opcode <= inst_in_s(6 downto 0);`
129			`funct3 <= inst_in_s(14 downto 12);`
130			`funct7 <= inst_in_s(31 downto 25);`
131			`rd <= inst_in_s(11 downto 7);`
132			`rs1 <= inst_in_s(19 downto 15);`
133			`rs2 <= inst_in_s(24 downto 20);`
134			`imm_i <= ext32(31 downto 12) & inst_in_s(31 downto 20);`
135			`imm_s <= ext32(31 downto 12) & inst_in_s(31 downto 25) & inst_in_s(11 downto 7);`
136			`imm_sb <= ext32(31 downto 13) & inst_in_s(31) & inst_in_s(7) & inst_in_s(30 downto 25) & inst_in_s(11 downto 8) & '0';`
137			`imm_u <= inst_in_s(31 downto 12);`
138			`imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0';`
139			`ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0');`
140
141			`-- control unit`
142	18	serginhofr	`control_unit: entity work.control`
143	13	serginhofr	`port map( opcode => opcode,`
144			`funct3 => funct3,`
145			`funct7 => funct7,`
146			`reg_write => reg_write_ctl,`
147			`alu_src1 => alu_src1_ctl,`
148			`alu_src2 => alu_src2_ctl,`
149			`alu_op => alu_op_ctl,`
150			`jump => jump_ctl,`
151			`branch => branch_ctl,`
152			`mem_write => mem_write_ctl,`
153			`mem_read => mem_read_ctl,`
154			`sig_read => sig_read_ctl`
155			`);`
156
157			`reg_to_mem <= '1' when mem_write_ctl /= "00" else '0';`
158			`mem_to_reg <= '1' when mem_read_ctl /= "00" else '0';`
159
160	18	serginhofr	`process(clock, reset, irq_ack_s, bds, mwait, stall)`
161	13	serginhofr	`begin`
162			`if reset = '1' then`
163			`rd_r <= (others => '0');`
164			`rs1_r <= (others => '0');`
165			`rs2_r <= (others => '0');`
166			`imm_i_r <= (others => '0');`
167			`imm_s_r <= (others => '0');`
168			`imm_sb_r <= (others => '0');`
169			`imm_u_r <= (others => '0');`
170			`imm_uj_r <= (others => '0');`
171			`reg_write_ctl_r <= '0';`
172			`alu_src1_ctl_r <= '0';`
173			`alu_src2_ctl_r <= (others => '0');`
174			`alu_op_ctl_r <= (others => '0');`
175			`jump_ctl_r <= (others => '0');`
176			`branch_ctl_r <= (others => '0');`
177			`mem_write_ctl_r <= (others => '0');`
178			`mem_read_ctl_r <= (others => '0');`
179			`sig_read_ctl_r <= '0';`
180			`reg_to_mem_r <= '0';`
181			`mem_to_reg_r <= '0';`
182			`elsif clock'event and clock = '1' then`
183			`if stall = '0' then`
184			`if irq_ack_s = '1' then`
185			`rd_r <= (others => '0');`
186			`rs1_r <= (others => '0');`
187			`rs2_r <= (others => '0');`
188			`imm_i_r <= (others => '0');`
189			`imm_s_r <= (others => '0');`
190			`imm_sb_r <= (others => '0');`
191			`imm_u_r <= (others => '0');`
192			`imm_uj_r <= (others => '0');`
193			`reg_write_ctl_r <= '0';`
194			`alu_src1_ctl_r <= '0';`
195			`alu_src2_ctl_r <= (others => '0');`
196			`alu_op_ctl_r <= (others => '0');`
197			`jump_ctl_r <= (others => '0');`
198			`branch_ctl_r <= (others => '0');`
199			`mem_write_ctl_r <= (others => '0');`
200			`mem_read_ctl_r <= (others => '0');`
201			`sig_read_ctl_r <= '0';`
202			`reg_to_mem_r <= '0';`
203			`mem_to_reg_r <= '0';`
204			`else`
205	18	serginhofr	`if mwait = '0' then`
206	17	serginhofr	`if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1' or branch_taken = '1' or jump_taken = '1' or bds = '1') then`
207	13	serginhofr	`rd_r <= (others => '0');`
208			`rs1_r <= (others => '0');`
209			`rs2_r <= (others => '0');`
210			`imm_i_r <= (others => '0');`
211			`imm_s_r <= (others => '0');`
212			`imm_sb_r <= (others => '0');`
213			`imm_u_r <= (others => '0');`
214			`imm_uj_r <= (others => '0');`
215			`reg_write_ctl_r <= '0';`
216			`alu_src1_ctl_r <= '0';`
217			`alu_src2_ctl_r <= (others => '0');`
218			`alu_op_ctl_r <= (others => '0');`
219			`jump_ctl_r <= (others => '0');`
220			`branch_ctl_r <= (others => '0');`
221			`mem_write_ctl_r <= (others => '0');`
222			`mem_read_ctl_r <= (others => '0');`
223			`sig_read_ctl_r <= '0';`
224			`reg_to_mem_r <= '0';`
225			`mem_to_reg_r <= '0';`
226			`else`
227			`rd_r <= rd;`
228			`rs1_r <= rs1;`
229			`rs2_r <= rs2;`
230			`imm_i_r <= imm_i;`
231			`imm_s_r <= imm_s;`
232			`imm_sb_r <= imm_sb;`
233			`imm_u_r <= imm_u;`
234			`imm_uj_r <= imm_uj;`
235			`reg_write_ctl_r <= reg_write_ctl;`
236			`alu_src1_ctl_r <= alu_src1_ctl;`
237			`alu_src2_ctl_r <= alu_src2_ctl;`
238			`alu_op_ctl_r <= alu_op_ctl;`
239			`jump_ctl_r <= jump_ctl;`
240			`branch_ctl_r <= branch_ctl;`
241			`mem_write_ctl_r <= mem_write_ctl;`
242			`mem_read_ctl_r <= mem_read_ctl;`
243			`sig_read_ctl_r <= sig_read_ctl;`
244			`reg_to_mem_r <= reg_to_mem;`
245			`mem_to_reg_r <= mem_to_reg;`
246			`end if;`
247			`end if;`
248			`end if;`
249			`end if;`
250			`end if;`
251			`end process;`
252
253			`--`
254			`-- EXECUTE STAGE`
255			`--`
256
257			`-- 3rd stage (a) register file access (read)`
258			`-- the register file`
259			`register_bank: entity work.reg_bank`
260			`port map( clock => clock,`
261			`read_reg1 => read_reg1,`
262			`read_reg2 => read_reg2,`
263			`write_reg => write_reg,`
264			`wreg => wreg,`
265			`write_data => write_data,`
266			`read_data1 => read_data1,`
267			`read_data2 => read_data2`
268			`);`
269
270			`-- register file read/write selection and write enable`
271			`read_reg1 <= rs1_r;`
272			`read_reg2 <= rs2_r;`
273			`write_reg <= rd_r;`
274	18	serginhofr	`wreg <= (reg_write_ctl_r or mem_to_reg_r_dly) and not mwait and not stall_reg;`
275	13	serginhofr
276			`-- 3rd stage (b) ALU operation`
277			`alu: entity work.alu`
278			`port map( op1 => alu_src1,`
279			`op2 => alu_src2,`
280			`alu_op => alu_op_ctl_r,`
281			`result => result,`
282			`zero => zero,`
283			`less_than => less_than`
284			`);`
285
286			`alu_src1 <= read_data1 when alu_src1_ctl_r = '0' else pc_last2;`
287			`alu_src2 <= imm_u_r & x"000" when alu_src2_ctl_r = "000" else`
288			`imm_i_r when alu_src2_ctl_r = "001" else`
289			`imm_s_r when alu_src2_ctl_r = "010" else`
290			`pc when alu_src2_ctl_r = "011" else`
291			`x"000000" & "000" & rs2_r when alu_src2_ctl_r = "100" else`
292			`read_data2;`
293
294			`branch_src1 <= read_data1 when jump_ctl_r = "11" else pc_last2;`
295			`branch_src2 <= imm_uj_r when jump_ctl_r = "10" else`
296			`imm_i_r when jump_ctl_r = "11" else imm_sb_r;`
297
298			`branch <= branch_src1 + branch_src2;`
299
300			`branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ`
301			`(zero = '0' and branch_ctl_r = "010") or -- BNE`
302			`(less_than = '1' and branch_ctl_r = "011") or -- BLT`
303			`(less_than = '0' and branch_ctl_r = "100") or -- BGE`
304			`(less_than = '1' and branch_ctl_r = "101") or -- BLTU`
305			`(less_than = '0' and branch_ctl_r = "110") -- BGEU`
306			`else '0';`
307			`except <= '1' when branch_ctl_r = "111" else '0';`
308			`jump_taken <= '1' when jump_ctl_r /= "00" else '0';`
309
310	18	serginhofr	`address <= result when data_access_s = '1' and mwait = '1' else pc;`
311			`data_access_s <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0';`
312			`mwait <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';`
313			`data_access <= mwait;`
314	13	serginhofr
315
316			`-- 3rd stage (c) data memory / write back operation, register file access (write)`
317			`-- memory access, store operations`
318			`process(mem_write_ctl_r, result, read_data2)`
319			`begin`
320			`case mem_write_ctl_r is`
321			`when "11" => -- store word`
322			`data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);`
323			`data_w <= "1111";`
324			`when "01" => -- store byte`
325			`data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);`
326			`case result(1 downto 0) is`
327			`when "11" => data_w <= "0001";`
328			`when "10" => data_w <= "0010";`
329			`when "01" => data_w <= "0100";`
330			`when others => data_w <= "1000";`
331			`end case;`
332			`when "10" => -- store half word`
333			`data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(7 downto 0) & read_data2(15 downto 8);`
334			`case result(1) is`
335			`when '1' => data_w <= "0011";`
336			`when others => data_w <= "1100";`
337			`end case;`
338			`when others => -- WTF??`
339			`data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);`
340			`data_w <= "0000";`
341			`end case;`
342			`end process;`
343
344			`-- memory access, load operations`
345			`process(mem_read_ctl_r, result, data_in)`
346			`begin`
347			`case mem_read_ctl_r is`
348			`when "01" => -- load byte`
349			`case result(1 downto 0) is`
350			`when "11" => data_in_s <= x"000000" & data_in(7 downto 0);`
351			`when "10" => data_in_s <= x"000000" & data_in(15 downto 8);`
352			`when "01" => data_in_s <= x"000000" & data_in(23 downto 16);`
353			`when others => data_in_s <= x"000000" & data_in(31 downto 24);`
354
355			`end case;`
356			`when "10" => -- load half word`
357			`case result(1) is`
358			`when '1' => data_in_s <= x"0000" & data_in(7 downto 0) & data_in(15 downto 8);`
359			`when others => data_in_s <= x"0000" & data_in(23 downto 16) & data_in(31 downto 24);`
360			`end case;`
361			`when others => -- load word`
362			`data_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);`
363			`end case;`
364			`end process;`
365
366			`-- write back`
367			`ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or sig_read_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);`
368			`ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or sig_read_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);`
369
370			`write_data <= data_in_s when mem_read_ctl_r = "11" else`
371			`ext32b when mem_read_ctl_r = "01" else`
372			`ext32h when mem_read_ctl_r = "10" else`
373			`pc_last when jump_taken = '1' else result;`
374
375			`end arch_datapath;`
376

Browse

Tools

Subversion Repositories hf-risc

[/] [hf-risc/] [trunk/] [hf-riscv/] [core_rv32i/] [datapath.vhd] - Blame information for rev 19