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[/] [hf-risc/] [trunk/] [hf-riscv/] [platform/] [spartan3_starterkit/] [spartan3_SRAM.vhd] - Blame information for rev 18

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hfrisc_soc is
        generic(
                address_width: integer := 14;
                memory_file : string := "code.txt";
                uart_support : string := "yes"
        );
        port (  clk_in:         in std_logic;
                reset_in:       in std_logic;
                int_in:         in std_logic;
                uart_read:      in std_logic;
                uart_write:     out std_logic;
 
                extio_in:       in std_logic_vector(7 downto 0);
                extio_out:      out std_logic_vector(7 downto 0);
 
                ram_address:    out std_logic_vector(31 downto 2);
                ram_data:       inout std_logic_vector(31 downto 0);
                ram_ce1_n:      out std_logic;
                ram_ub1_n:      out std_logic;
                ram_lb1_n:      out std_logic;
                ram_ce2_n:      out std_logic;
                ram_ub2_n:      out std_logic;
                ram_lb2_n:      out std_logic;
                ram_we_n:       out std_logic;
                ram_oe_n:       out std_logic
        );
end hfrisc_soc;
 
architecture top_level of hfrisc_soc is
        signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
        signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
        signal data_we, data_w_cpu: std_logic_vector(3 downto 0);
 
        signal we_n_next    : std_logic;
        signal we_n_reg     : std_logic;
        signal data_reg     : std_logic_vector(31 downto 0);
begin
        -- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
        process (reset_in, clk_in, clock, we_n_next)
        begin
                if reset_in = '1' then
                        clock <= '0';
                else
                        if clk_in'event and clk_in='1' then
                                clock <= not clock;
                        end if;
                end if;
 
                if reset_in = '1' then
                        we_n_reg <= '1';
                elsif rising_edge(clk_in) then
                        we_n_reg <= we_n_next or not clock;
                end if;
 
                if reset_in = '1' then
                        data_read_ram <= (others => '0');
                elsif rising_edge(clock) then
                        data_read_ram <= ram_data;
                end if;
        end process;
 
        -- reset synchronizer
        process (clock, reset_in)
        begin
                if (reset_in = '1') then
                        rff1 <= '1';
                        reset <= '1';
                elsif (clock'event and clock = '1') then
                        rff1 <= '0';
                        reset <= rff1;
                end if;
        end process;
 
 
        process (reset, clock, ram_enable_n)
        begin
                if reset = '1' then
                        ram_dly <= '0';
                elsif clock'event and clock = '1' then
                        ram_dly <= not ram_enable_n;
                end if;
        end process;
 
        stall <= '0';
        boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
        data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
 
        -- HF-RISC core
        core: entity work.datapath
        port map(       clock => clock,
                        reset => reset,
                        stall => stall_cpu,
                        irq_vector => irq_vector_cpu,
                        irq => irq_cpu,
                        irq_ack => irq_ack_cpu,
                        exception => exception_cpu,
                        address => address_cpu,
                        data_in => data_in_cpu,
                        data_out => data_out_cpu,
                        data_w => data_w_cpu,
                        data_access => data_access_cpu
        );
 
        -- peripherals / busmux logic
        peripherals_busmux: entity work.busmux
        generic map(
                uart_support => uart_support
        )
        port map(
                clock => clock,
                reset => reset,
 
                stall => stall,
 
                stall_cpu => stall_cpu,
                irq_vector_cpu => irq_vector_cpu,
                irq_cpu => irq_cpu,
                irq_ack_cpu => irq_ack_cpu,
                exception_cpu => exception_cpu,
                address_cpu => address_cpu,
                data_in_cpu => data_in_cpu,
                data_out_cpu => data_out_cpu,
                data_w_cpu => data_w_cpu,
                data_access_cpu => data_access_cpu,
 
                addr_mem => address,
                data_read_mem => data_read,
                data_write_mem => data_write,
                data_we_mem => data_we,
                extio_in => extio_in,
                extio_out => extio_out,
                uart_read => uart_read,
                uart_write => uart_write
        );
 
        -- instruction and data memory (boot RAM)
        boot_ram: entity work.ram
        generic map (memory_type => "DEFAULT")
        port map (
                clk                     => clock,
                enable                  => boot_enable,
                write_byte_enable       => "0000",
                address                 => address(31 downto 2),
                data_write              => (others => '0'),
                data_read               => data_read_boot
        );
 
        -- instruction and data memory (external SRAM)
        -- very simple SRAM memory controller using both IS61LV25616AL chips.
        -- these SRAMs have 16-bit words, so we use both chips and access each using low and
        -- high banks. using this arrangement, we have byte addressable 32-bit words.
        -- the address bus is controlled directly by the CPU.
        ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
        ram_address <= address(31 downto 2);
        ram_we_n <= we_n_reg;
 
        ram_control:
        process(clock, ram_enable_n, data_we, data_write)
        begin
                if ram_enable_n = '0' then                       --SRAM
                        ram_ce1_n <= '0';
                        ram_ce2_n <= '0';
                        if data_we = "0000" then                -- read
                                ram_data  <= (others => 'Z');
                                ram_ub1_n <= '0';
                                ram_lb1_n <= '0';
                                ram_ub2_n <= '0';
                                ram_lb2_n <= '0';
                                we_n_next <= '1';
                                ram_oe_n  <= '0';
                        else                                    -- write
                                if clock = '1' then
                                        ram_data <= (others => 'Z');
                                else
                                        ram_data <= data_write;
                                end if;
                                ram_ub1_n <= not data_we(3);
                                ram_lb1_n <= not data_we(2);
                                ram_ub2_n <= not data_we(1);
                                ram_lb2_n <= not data_we(0);
                                we_n_next <= '0';
                                ram_oe_n  <= '1';
                        end if;
                else
                        ram_data <= (others => 'Z');
                        ram_ce1_n <= '1';
                        ram_ub1_n <= '1';
                        ram_lb1_n <= '1';
                        ram_ce2_n <= '1';
                        ram_ub2_n <= '1';
                        ram_lb2_n <= '1';
                        we_n_next <= '1';
                        ram_oe_n  <= '1';
                end if;
        end process;
 
end top_level;
 

Line No.	Rev	Author	Line
1	13	serginhofr	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_unsigned.all;`
4
5	18	serginhofr	`entity hfrisc_soc is`
6	13	serginhofr	`generic(`
7			`address_width: integer := 14;`
8			`memory_file : string := "code.txt";`
9			`uart_support : string := "yes"`
10			`);`
11			`port ( clk_in: in std_logic;`
12			`reset_in: in std_logic;`
13			`int_in: in std_logic;`
14			`uart_read: in std_logic;`
15			`uart_write: out std_logic;`
16
17	18	serginhofr	`extio_in: in std_logic_vector(7 downto 0);`
18			`extio_out: out std_logic_vector(7 downto 0);`
19
20	13	serginhofr	`ram_address: out std_logic_vector(31 downto 2);`
21			`ram_data: inout std_logic_vector(31 downto 0);`
22			`ram_ce1_n: out std_logic;`
23			`ram_ub1_n: out std_logic;`
24			`ram_lb1_n: out std_logic;`
25			`ram_ce2_n: out std_logic;`
26			`ram_ub2_n: out std_logic;`
27			`ram_lb2_n: out std_logic;`
28			`ram_we_n: out std_logic;`
29			`ram_oe_n: out std_logic`
30			`);`
31	18	serginhofr	`end hfrisc_soc;`
32	13	serginhofr
33	18	serginhofr	`architecture top_level of hfrisc_soc is`
34			`signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;`
35			`signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);`
36	13	serginhofr	`signal data_we, data_w_cpu: std_logic_vector(3 downto 0);`
37
38			`signal we_n_next : std_logic;`
39			`signal we_n_reg : std_logic;`
40			`signal data_reg : std_logic_vector(31 downto 0);`
41			`begin`
42			`-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)`
43	18	serginhofr	`process (reset_in, clk_in, clock, we_n_next)`
44	13	serginhofr	`begin`
45			`if reset_in = '1' then`
46			`clock <= '0';`
47			`else`
48			`if clk_in'event and clk_in='1' then`
49			`clock <= not clock;`
50			`end if;`
51			`end if;`
52	18	serginhofr
53			`if reset_in = '1' then`
54			`we_n_reg <= '1';`
55			`elsif rising_edge(clk_in) then`
56			`we_n_reg <= we_n_next or not clock;`
57			`end if;`
58
59			`if reset_in = '1' then`
60			`data_read_ram <= (others => '0');`
61			`elsif rising_edge(clock) then`
62			`data_read_ram <= ram_data;`
63			`end if;`
64	13	serginhofr	`end process;`
65
66			`-- reset synchronizer`
67			`process (clock, reset_in)`
68			`begin`
69			`if (reset_in = '1') then`
70			`rff1 <= '1';`
71			`reset <= '1';`
72			`elsif (clock'event and clock = '1') then`
73			`rff1 <= '0';`
74			`reset <= rff1;`
75			`end if;`
76			`end process;`
77
78	18	serginhofr
79			`process (reset, clock, ram_enable_n)`
80	13	serginhofr	`begin`
81			`if reset = '1' then`
82			`ram_dly <= '0';`
83			`elsif clock'event and clock = '1' then`
84			`ram_dly <= not ram_enable_n;`
85			`end if;`
86			`end process;`
87
88			`stall <= '0';`
89			`boot_enable <= '1' when address(31 downto 28) = "0000" else '0';`
90			`data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;`
91
92	18	serginhofr	`-- HF-RISC core`
93	13	serginhofr	`core: entity work.datapath`
94			`port map( clock => clock,`
95			`reset => reset,`
96			`stall => stall_cpu,`
97			`irq_vector => irq_vector_cpu,`
98			`irq => irq_cpu,`
99			`irq_ack => irq_ack_cpu,`
100			`exception => exception_cpu,`
101	18	serginhofr	`address => address_cpu,`
102	13	serginhofr	`data_in => data_in_cpu,`
103			`data_out => data_out_cpu,`
104			`data_w => data_w_cpu,`
105			`data_access => data_access_cpu`
106			`);`
107
108			`-- peripherals / busmux logic`
109			`peripherals_busmux: entity work.busmux`
110			`generic map(`
111			`uart_support => uart_support`
112			`)`
113			`port map(`
114			`clock => clock,`
115			`reset => reset,`
116
117			`stall => stall,`
118
119			`stall_cpu => stall_cpu,`
120			`irq_vector_cpu => irq_vector_cpu,`
121			`irq_cpu => irq_cpu,`
122			`irq_ack_cpu => irq_ack_cpu,`
123			`exception_cpu => exception_cpu,`
124	18	serginhofr	`address_cpu => address_cpu,`
125	13	serginhofr	`data_in_cpu => data_in_cpu,`
126			`data_out_cpu => data_out_cpu,`
127			`data_w_cpu => data_w_cpu,`
128			`data_access_cpu => data_access_cpu,`
129
130			`addr_mem => address,`
131			`data_read_mem => data_read,`
132			`data_write_mem => data_write,`
133			`data_we_mem => data_we,`
134	18	serginhofr	`extio_in => extio_in,`
135			`extio_out => extio_out,`
136	13	serginhofr	`uart_read => uart_read,`
137			`uart_write => uart_write`
138			`);`
139
140			`-- instruction and data memory (boot RAM)`
141			`boot_ram: entity work.ram`
142			`generic map (memory_type => "DEFAULT")`
143			`port map (`
144			`clk => clock,`
145			`enable => boot_enable,`
146			`write_byte_enable => "0000",`
147			`address => address(31 downto 2),`
148			`data_write => (others => '0'),`
149			`data_read => data_read_boot`
150			`);`
151
152			`-- instruction and data memory (external SRAM)`
153			`-- very simple SRAM memory controller using both IS61LV25616AL chips.`
154			`-- these SRAMs have 16-bit words, so we use both chips and access each using low and`
155			`-- high banks. using this arrangement, we have byte addressable 32-bit words.`
156			`-- the address bus is controlled directly by the CPU.`
157			`ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';`
158			`ram_address <= address(31 downto 2);`
159	18	serginhofr	`ram_we_n <= we_n_reg;`
160	13	serginhofr
161			`ram_control:`
162			`process(clock, ram_enable_n, data_we, data_write)`
163			`begin`
164			`if ram_enable_n = '0' then --SRAM`
165			`ram_ce1_n <= '0';`
166			`ram_ce2_n <= '0';`
167			`if data_we = "0000" then -- read`
168			`ram_data <= (others => 'Z');`
169			`ram_ub1_n <= '0';`
170			`ram_lb1_n <= '0';`
171			`ram_ub2_n <= '0';`
172			`ram_lb2_n <= '0';`
173	18	serginhofr	`we_n_next <= '1';`
174	13	serginhofr	`ram_oe_n <= '0';`
175			`else -- write`
176	18	serginhofr	`if clock = '1' then`
177			`ram_data <= (others => 'Z');`
178			`else`
179			`ram_data <= data_write;`
180			`end if;`
181	13	serginhofr	`ram_ub1_n <= not data_we(3);`
182			`ram_lb1_n <= not data_we(2);`
183			`ram_ub2_n <= not data_we(1);`
184			`ram_lb2_n <= not data_we(0);`
185	18	serginhofr	`we_n_next <= '0';`
186	13	serginhofr	`ram_oe_n <= '1';`
187			`end if;`
188			`else`
189			`ram_data <= (others => 'Z');`
190			`ram_ce1_n <= '1';`
191			`ram_ub1_n <= '1';`
192			`ram_lb1_n <= '1';`
193			`ram_ce2_n <= '1';`
194			`ram_ub2_n <= '1';`
195			`ram_lb2_n <= '1';`
196	18	serginhofr	`we_n_next <= '1';`
197	13	serginhofr	`ram_oe_n <= '1';`
198			`end if;`
199			`end process;`
200
201	18	serginhofr	`end top_level;`
202	13	serginhofr

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[/] [hf-risc/] [trunk/] [hf-riscv/] [platform/] [spartan3_starterkit/] [spartan3_SRAM.vhd] - Blame information for rev 18