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[/] [hf-risc/] [trunk/] [software/] [lib/] [mips/] [crt0.s] - Blame information for rev 18

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Line No.	Rev	Author	Line
1	13	serginhofr	`# file: crt0.s`
2			`# description: basic C runtime for HF-RISC`
3			`# date: 09/2015`
4			`# author: Sergio Johann Filho <sergio.filho@pucrs.br>`
5
6			`.text`
7			`.align 2`
8
9			`.global _entry`
10			`.ent _entry`
11			`_entry:`
12			`.set noreorder`
13			`.set noat`
14
15			`la $a1, _bss_start`
16			`la $a0, _end`
17			`la $gp, _gp`
18			`la $sp, _stack`
19
20			`$BSS_CLEAR:`
21			`# clear the .bss`
22			`sw $zero, 0($a1)`
23			`slt $v1, $a1, $a0`
24			`addiu $a1, $a1, 4`
25			`bnez $v1, $BSS_CLEAR`
26			`nop`
27
28			`# configure IRQ_VECTOR`
29			`la $k1, _isr`
30			`li $k0, 0xf0000000`
31			`sw $k1, 0($k0)`
32
33			`# jump to main`
34			`jal main`
35			`nop`
36
37			`li $k0, 0xe0000000 # this will interrupt the simulation (assertion)`
38			`sw $zero, 0($k0)`
39
40			`$L1:`
41			`beq $zero, $zero, $L1`
42			`nop`
43			`.end _entry`
44
45			`# the non-vectored interrupt service routine`
46			`.org 0x100`
47			`.global _isr`
48			`.ent _isr`
49			`_isr:`
50			`.set noreorder`
51			`.set noat`
52
53			`nop # this must be a NOP`
54			`# save all temporary registers`
55			`addiu $sp, $sp, -104`
56			`sw $at, 16($sp)`
57			`sw $v0, 20($sp)`
58			`sw $v1, 24($sp)`
59			`sw $a0, 28($sp)`
60			`sw $a1, 32($sp)`
61			`sw $a2, 36($sp)`
62			`sw $a3, 40($sp)`
63			`sw $t0, 44($sp)`
64			`sw $t1, 48($sp)`
65			`sw $t2, 52($sp)`
66			`sw $t3, 56($sp)`
67			`sw $t4, 60($sp)`
68			`sw $t5, 64($sp)`
69			`sw $t6, 68($sp)`
70			`sw $t7, 72($sp)`
71			`sw $t8, 76($sp)`
72			`sw $t9, 80($sp)`
73			`sw $ra, 84($sp)`
74			`li $k0, 0xf0000040 # read IRQ_EPC`
75			`lw $k0, 0($k0)`
76			`addiu $k0, $k0, -4 # last instruction was not commited, rollback!`
77			`sw $k0, 88($sp)`
78			`mfhi $k1`
79			`sw $k1, 92($sp)`
80			`mflo $k1`
81			`sw $k1, 96($sp)`
82			`lui $a1, 0xf000`
83			`lw $a0, 0x10($a1) # read IRQ_CAUSE`
84			`lw $a2, 0x20($a1) # read IRQ_MASK`
85			`and $a0, $a0, $a2 # pass CAUSE and MASK and the stack pointer to the C handler`
86			`jal interrupt_handler # jump to C handler`
87			`addiu $a1, $sp, 0`
88
89			`# restore all temporary registers`
90			`lw $at, 16($sp)`
91			`lw $v0, 20($sp)`
92			`lw $v1, 24($sp)`
93			`lw $a0, 28($sp)`
94			`lw $a1, 32($sp)`
95			`lw $a2, 36($sp)`
96			`lw $a3, 40($sp)`
97			`lw $t0, 44($sp)`
98			`lw $t1, 48($sp)`
99			`lw $t2, 52($sp)`
100			`lw $t3, 56($sp)`
101			`lw $t4, 60($sp)`
102			`lw $t5, 64($sp)`
103			`lw $t6, 68($sp)`
104			`lw $t7, 72($sp)`
105			`lw $t8, 76($sp)`
106			`lw $t9, 80($sp)`
107			`lw $ra, 84($sp)`
108			`lw $k0, 88($sp)`
109			`lw $k1, 92($sp)`
110			`mthi $k1`
111			`lw $k1, 96($sp)`
112			`mtlo $k1`
113			`addiu $sp, $sp, 104`
114			`ori $k1, $zero, 0x1`
115			`li $k0, 0xf0000030`
116			`sw $k1, 0($k0) # enable interrupts after a few cycles`
117			`lw $k0, -16($sp)`
118			`jr $k0 # context restored, continue`
119			`nop`
120
121			`.end _isr`
122
123			`.set at`
124			`.align 2`
125
126			`.global _interrupt_set`
127			`.ent _interrupt_set`
128			`_interrupt_set:`
129			`.set noreorder`
130
131			`li $v1, 0xf0000030`
132			`lw $v0, 0($v1)`
133			`jr $ra`
134			`sw $a0, 0($v1)`
135
136			`.set reorder`
137			`.end _interrupt_set`
138
139			`.global setjmp`
140			`.ent setjmp`
141			`setjmp:`
142			`.set noreorder`
143
144			`sw $s0, 0($a0)`
145			`sw $s1, 4($a0)`
146			`sw $s2, 8($a0)`
147			`sw $s3, 12($a0)`
148			`sw $s4, 16($a0)`
149			`sw $s5, 20($a0)`
150			`sw $s6, 24($a0)`
151			`sw $s7, 28($a0)`
152			`sw $fp, 32($a0)`
153			`sw $gp, 36($a0)`
154			`sw $sp, 40($a0)`
155			`sw $ra, 44($a0)`
156
157			`jr $ra`
158			`ori $v0, $zero, 0`
159
160			`.set reorder`
161			`.end setjmp`
162
163
164			`.global longjmp`
165			`.ent longjmp`
166			`longjmp:`
167			`.set noreorder`
168
169			`lw $s0, 0($a0)`
170			`lw $s1, 4($a0)`
171			`lw $s2, 8($a0)`
172			`lw $s3, 12($a0)`
173			`lw $s4, 16($a0)`
174			`lw $s5, 20($a0)`
175			`lw $s6, 24($a0)`
176			`lw $s7, 28($a0)`
177			`lw $fp, 32($a0)`
178			`lw $gp, 36($a0)`
179			`lw $sp, 40($a0)`
180			`lw $ra, 44($a0)`
181
182			`jr $ra`
183			`ori $v0, $a1, 0`
184
185			`.set reorder`
186			`.end longjmp`
187

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[/] [hf-risc/] [trunk/] [software/] [lib/] [mips/] [crt0.s] - Blame information for rev 18