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[/] [hf-risc/] [trunk/] [software/] [lib/] [riscv/] [crt0.s] - Blame information for rev 16

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Line No.	Rev	Author	Line
1	13	serginhofr	`.text`
2			`.align 2`
3
4			`.global _entry`
5			`_entry:`
6			`la a3, _bss_start`
7			`la a2, _end`
8			`la gp, _gp`
9			`la sp, _stack`
10			`la tp, _end + 63`
11			`and tp, tp, -64`
12
13			`BSS_CLEAR:`
14			`# clear the .bss`
15			`sw zero, 0(a3)`
16			`addi a3, a3, 4`
17			`blt a3, a2, BSS_CLEAR`
18
19			`# configure IRQ_VECTOR`
20			`la s11, _isr`
21			`li s10, 0xf0000000`
22			`sw s11, 0(s10)`
23
24			`# jump to main`
25			`jal ra, main`
26
27			`li s10, 0xe0000000 # this will interrupt the simulation (assertion)`
28			`sw zero, 0(s10)`
29
30			`L1:`
31			`beq zero, zero, L1`
32
33			`# interrupt / exception service routine`
34			`.org 0x100`
35			`.global _isr`
36			`_isr:`
37			`nop # this must be a NOP`
38			`addi sp, sp, -68`
39			`sw ra, 0(sp)`
40			`sw t0, 4(sp)`
41			`sw t1, 8(sp)`
42			`sw t2, 12(sp)`
43			`sw a0, 16(sp)`
44			`sw a1, 20(sp)`
45			`sw a2, 24(sp)`
46			`sw a3, 28(sp)`
47			`sw a4, 32(sp)`
48			`sw a5, 36(sp)`
49			`sw a6, 40(sp)`
50			`sw a7, 44(sp)`
51			`sw t3, 48(sp)`
52			`sw t4, 52(sp)`
53			`sw t5, 56(sp)`
54			`sw t6, 60(sp)`
55			`li s10, 0xf0000040 # read IRQ_EPC`
56			`lw s10, 0(s10)`
57			`addi s10, s10, -4 # rollback, last opcode (at EPC) was not commited`
58			`sw s10, 64(sp)`
59			`lui a1, 0xf0000`
60			`lw a0, 0x10(a1) # read IRQ_CAUSE`
61			`lw a2, 0x20(a1) # read IRQ_MASK`
62			`and a0, a0, a2 # pass CAUSE and MASK and the stack pointer to the C handler`
63			`addi a1, sp, 0`
64			`beq a0, zero, _exception # it's an exception, not an interrupt`
65			`jal ra, interrupt_handler # jump to C handler`
66			`_restore:`
67			`lw ra, 0(sp)`
68			`lw t0, 4(sp)`
69			`lw t1, 8(sp)`
70			`lw t2, 12(sp)`
71			`lw a0, 16(sp)`
72			`lw a1, 20(sp)`
73			`lw a2, 24(sp)`
74			`lw a3, 28(sp)`
75			`lw a4, 32(sp)`
76			`lw a5, 36(sp)`
77			`lw a6, 40(sp)`
78			`lw a7, 44(sp)`
79			`lw t3, 48(sp)`
80			`lw t4, 52(sp)`
81			`lw t5, 56(sp)`
82			`lw t6, 60(sp)`
83			`addi sp, sp, 68`
84			`ori s11, zero, 0x1`
85			`li s10, 0xf0000030`
86			`sw s11, 0(s10) # enable interrupts after a few cycles`
87			`lw s10, -4(sp)`
88			`jalr zero, s10 # context restored, continue`
89			`_exception:`
90			`addi s10, s10, -4 # s10 is IRQ_EPC-4, actual EPC is IRQ_EPC-8`
91			`lw s11, 0(s10) # read opcode`
92			`addi a0, s10, 0`
93			`addi a1, s11, 0`
94			`jal ra, exception_handler # TODO: set rd reg on some exceptions`
95			`jal zero, _restore`
96
97			`.global _interrupt_set`
98			`_interrupt_set:`
99			`li a1, 0xf0000030`
100			`lw a2, 0(a1)`
101			`sw a0, 0(a1)`
102			`addi a0, a2, 0`
103			`ret`
104
105			`.global setjmp`
106			`setjmp:`
107			`sw s0, 0(a0)`
108			`sw s1, 4(a0)`
109			`sw s2, 8(a0)`
110			`sw s3, 12(a0)`
111			`sw s4, 16(a0)`
112			`sw s5, 20(a0)`
113			`sw s6, 24(a0)`
114			`sw s7, 28(a0)`
115			`sw s8, 32(a0)`
116			`sw s9, 36(a0)`
117			`# sw gp, 40(a0)`
118			`sw tp, 44(a0)`
119			`sw sp, 48(a0)`
120			`sw ra, 52(a0)`
121			`ori a0, zero, 0`
122			`ret`
123
124			`.global longjmp`
125			`longjmp:`
126			`lw s0, 0(a0)`
127			`lw s1, 4(a0)`
128			`lw s2, 8(a0)`
129			`lw s3, 12(a0)`
130			`lw s4, 16(a0)`
131			`lw s5, 20(a0)`
132			`lw s6, 24(a0)`
133			`lw s7, 28(a0)`
134			`lw s8, 32(a0)`
135			`lw s9, 36(a0)`
136			`# lw gp, 40(a0)`
137			`lw tp, 44(a0)`
138			`lw sp, 48(a0)`
139			`lw ra, 52(a0)`
140			`ori a0, a1, 0`
141			`ret`

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[/] [hf-risc/] [trunk/] [software/] [lib/] [riscv/] [crt0.s] - Blame information for rev 16