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13 |
serginhofr |
/* Automatically generated by parse-opcodes */
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#ifndef RISCV_ENCODING_H
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#define RISCV_ENCODING_H
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#define MATCH_SLLI_RV32 0x1013
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#define MASK_SLLI_RV32 0xfe00707f
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#define MATCH_SRLI_RV32 0x5013
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#define MASK_SRLI_RV32 0xfe00707f
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#define MATCH_SRAI_RV32 0x40005013
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#define MASK_SRAI_RV32 0xfe00707f
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#define MATCH_FRFLAGS 0x102073
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#define MASK_FRFLAGS 0xfffff07f
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#define MATCH_FSFLAGS 0x101073
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#define MASK_FSFLAGS 0xfff0707f
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#define MATCH_FSFLAGSI 0x105073
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#define MASK_FSFLAGSI 0xfff0707f
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#define MATCH_FRRM 0x202073
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#define MASK_FRRM 0xfffff07f
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#define MATCH_FSRM 0x201073
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#define MASK_FSRM 0xfff0707f
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#define MATCH_FSRMI 0x205073
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#define MASK_FSRMI 0xfff0707f
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#define MATCH_FSCSR 0x301073
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#define MASK_FSCSR 0xfff0707f
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#define MATCH_FRCSR 0x302073
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#define MASK_FRCSR 0xfffff07f
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#define MATCH_RDCYCLE 0xc0002073
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#define MASK_RDCYCLE 0xfffff07f
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#define MATCH_RDTIME 0xc0102073
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#define MASK_RDTIME 0xfffff07f
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#define MATCH_RDINSTRET 0xc0202073
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#define MASK_RDINSTRET 0xfffff07f
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#define MATCH_RDCYCLEH 0xc8002073
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#define MASK_RDCYCLEH 0xfffff07f
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#define MATCH_RDTIMEH 0xc8102073
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#define MASK_RDTIMEH 0xfffff07f
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#define MATCH_RDINSTRETH 0xc8202073
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#define MASK_RDINSTRETH 0xfffff07f
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#define MATCH_ECALL 0x73
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#define MASK_ECALL 0xffffffff
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#define MATCH_EBREAK 0x100073
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#define MASK_EBREAK 0xffffffff
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#define MATCH_ERET 0x10000073
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#define MASK_ERET 0xffffffff
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#define MATCH_BEQ 0x63
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#define MASK_BEQ 0x707f
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#define MATCH_BNE 0x1063
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#define MASK_BNE 0x707f
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#define MATCH_BLT 0x4063
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#define MASK_BLT 0x707f
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#define MATCH_BGE 0x5063
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#define MASK_BGE 0x707f
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#define MATCH_BLTU 0x6063
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#define MASK_BLTU 0x707f
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#define MATCH_BGEU 0x7063
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#define MASK_BGEU 0x707f
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#define MATCH_JALR 0x67
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#define MASK_JALR 0x707f
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#define MATCH_JAL 0x6f
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#define MASK_JAL 0x7f
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#define MATCH_LUI 0x37
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#define MASK_LUI 0x7f
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#define MATCH_AUIPC 0x17
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#define MASK_AUIPC 0x7f
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#define MATCH_ADDI 0x13
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#define MASK_ADDI 0x707f
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#define MATCH_SLLI 0x1013
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#define MASK_SLLI 0xfc00707f
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#define MATCH_SLTI 0x2013
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#define MASK_SLTI 0x707f
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#define MATCH_SLTIU 0x3013
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#define MASK_SLTIU 0x707f
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#define MATCH_XORI 0x4013
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#define MASK_XORI 0x707f
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#define MATCH_SRLI 0x5013
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#define MASK_SRLI 0xfc00707f
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#define MATCH_SRAI 0x40005013
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#define MASK_SRAI 0xfc00707f
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#define MATCH_ORI 0x6013
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#define MASK_ORI 0x707f
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#define MATCH_ANDI 0x7013
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#define MASK_ANDI 0x707f
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#define MATCH_ADD 0x33
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#define MASK_ADD 0xfe00707f
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#define MATCH_SUB 0x40000033
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#define MASK_SUB 0xfe00707f
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#define MATCH_SLL 0x1033
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#define MASK_SLL 0xfe00707f
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#define MATCH_SLT 0x2033
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#define MASK_SLT 0xfe00707f
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#define MATCH_SLTU 0x3033
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#define MASK_SLTU 0xfe00707f
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#define MATCH_XOR 0x4033
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#define MASK_XOR 0xfe00707f
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#define MATCH_SRL 0x5033
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#define MASK_SRL 0xfe00707f
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#define MATCH_SRA 0x40005033
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#define MASK_SRA 0xfe00707f
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#define MATCH_OR 0x6033
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#define MASK_OR 0xfe00707f
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#define MATCH_AND 0x7033
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#define MASK_AND 0xfe00707f
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#define MATCH_ADDIW 0x1b
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#define MASK_ADDIW 0x707f
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#define MATCH_SLLIW 0x101b
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#define MASK_SLLIW 0xfe00707f
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#define MATCH_SRLIW 0x501b
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#define MASK_SRLIW 0xfe00707f
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#define MATCH_SRAIW 0x4000501b
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#define MASK_SRAIW 0xfe00707f
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#define MATCH_ADDW 0x3b
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#define MASK_ADDW 0xfe00707f
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#define MATCH_SUBW 0x4000003b
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#define MASK_SUBW 0xfe00707f
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#define MATCH_SLLW 0x103b
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#define MASK_SLLW 0xfe00707f
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#define MATCH_SRLW 0x503b
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#define MASK_SRLW 0xfe00707f
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#define MATCH_SRAW 0x4000503b
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#define MASK_SRAW 0xfe00707f
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#define MATCH_LB 0x3
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#define MASK_LB 0x707f
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#define MATCH_LH 0x1003
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#define MASK_LH 0x707f
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#define MATCH_LW 0x2003
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#define MASK_LW 0x707f
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#define MATCH_LD 0x3003
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#define MASK_LD 0x707f
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#define MATCH_LBU 0x4003
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#define MASK_LBU 0x707f
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#define MATCH_LHU 0x5003
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#define MASK_LHU 0x707f
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#define MATCH_LWU 0x6003
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#define MASK_LWU 0x707f
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#define MATCH_SB 0x23
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#define MASK_SB 0x707f
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#define MATCH_SH 0x1023
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#define MASK_SH 0x707f
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#define MATCH_SW 0x2023
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#define MASK_SW 0x707f
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#define MATCH_SD 0x3023
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#define MASK_SD 0x707f
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#define MATCH_FENCE 0xf
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#define MASK_FENCE 0x707f
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#define MATCH_FENCE_I 0x100f
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#define MASK_FENCE_I 0x707f
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#define MATCH_MUL 0x2000033
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#define MASK_MUL 0xfe00707f
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#define MATCH_MULH 0x2001033
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#define MASK_MULH 0xfe00707f
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#define MATCH_MULHSU 0x2002033
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#define MASK_MULHSU 0xfe00707f
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#define MATCH_MULHU 0x2003033
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| 153 |
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#define MASK_MULHU 0xfe00707f
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#define MATCH_DIV 0x2004033
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#define MASK_DIV 0xfe00707f
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#define MATCH_DIVU 0x2005033
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| 157 |
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#define MASK_DIVU 0xfe00707f
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| 158 |
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#define MATCH_REM 0x2006033
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| 159 |
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#define MASK_REM 0xfe00707f
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| 160 |
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#define MATCH_REMU 0x2007033
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| 161 |
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#define MASK_REMU 0xfe00707f
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| 162 |
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#define MATCH_MULW 0x200003b
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| 163 |
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#define MASK_MULW 0xfe00707f
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| 164 |
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#define MATCH_DIVW 0x200403b
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| 165 |
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#define MASK_DIVW 0xfe00707f
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| 166 |
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#define MATCH_DIVUW 0x200503b
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| 167 |
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#define MASK_DIVUW 0xfe00707f
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| 168 |
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#define MATCH_REMW 0x200603b
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| 169 |
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#define MASK_REMW 0xfe00707f
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| 170 |
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#define MATCH_REMUW 0x200703b
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| 171 |
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#define MASK_REMUW 0xfe00707f
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| 172 |
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#define MATCH_AMOADD_W 0x202f
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| 173 |
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#define MASK_AMOADD_W 0xf800707f
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| 174 |
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#define MATCH_AMOXOR_W 0x2000202f
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#define MASK_AMOXOR_W 0xf800707f
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| 176 |
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#define MATCH_AMOOR_W 0x4000202f
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| 177 |
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#define MASK_AMOOR_W 0xf800707f
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| 178 |
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#define MATCH_AMOAND_W 0x6000202f
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| 179 |
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#define MASK_AMOAND_W 0xf800707f
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| 180 |
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#define MATCH_AMOMIN_W 0x8000202f
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| 181 |
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#define MASK_AMOMIN_W 0xf800707f
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| 182 |
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#define MATCH_AMOMAX_W 0xa000202f
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| 183 |
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#define MASK_AMOMAX_W 0xf800707f
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| 184 |
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#define MATCH_AMOMINU_W 0xc000202f
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| 185 |
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#define MASK_AMOMINU_W 0xf800707f
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| 186 |
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#define MATCH_AMOMAXU_W 0xe000202f
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| 187 |
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#define MASK_AMOMAXU_W 0xf800707f
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| 188 |
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#define MATCH_AMOSWAP_W 0x800202f
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| 189 |
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#define MASK_AMOSWAP_W 0xf800707f
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| 190 |
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#define MATCH_LR_W 0x1000202f
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| 191 |
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#define MASK_LR_W 0xf9f0707f
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| 192 |
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#define MATCH_SC_W 0x1800202f
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| 193 |
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#define MASK_SC_W 0xf800707f
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| 194 |
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#define MATCH_AMOADD_D 0x302f
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| 195 |
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#define MASK_AMOADD_D 0xf800707f
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| 196 |
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#define MATCH_AMOXOR_D 0x2000302f
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| 197 |
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#define MASK_AMOXOR_D 0xf800707f
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| 198 |
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#define MATCH_AMOOR_D 0x4000302f
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| 199 |
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#define MASK_AMOOR_D 0xf800707f
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| 200 |
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#define MATCH_AMOAND_D 0x6000302f
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| 201 |
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#define MASK_AMOAND_D 0xf800707f
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| 202 |
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#define MATCH_AMOMIN_D 0x8000302f
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| 203 |
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#define MASK_AMOMIN_D 0xf800707f
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| 204 |
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#define MATCH_AMOMAX_D 0xa000302f
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| 205 |
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#define MASK_AMOMAX_D 0xf800707f
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| 206 |
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#define MATCH_AMOMINU_D 0xc000302f
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| 207 |
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#define MASK_AMOMINU_D 0xf800707f
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| 208 |
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#define MATCH_AMOMAXU_D 0xe000302f
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| 209 |
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#define MASK_AMOMAXU_D 0xf800707f
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| 210 |
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#define MATCH_AMOSWAP_D 0x800302f
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| 211 |
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#define MASK_AMOSWAP_D 0xf800707f
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| 212 |
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#define MATCH_LR_D 0x1000302f
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| 213 |
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#define MASK_LR_D 0xf9f0707f
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| 214 |
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#define MATCH_SC_D 0x1800302f
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| 215 |
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#define MASK_SC_D 0xf800707f
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| 216 |
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#define MATCH_SCALL 0x73
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| 217 |
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#define MASK_SCALL 0xffffffff
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| 218 |
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#define MATCH_SBREAK 0x100073
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| 219 |
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#define MASK_SBREAK 0xffffffff
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| 220 |
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#define MATCH_SRET 0x10000073
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| 221 |
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#define MASK_SRET 0xffffffff
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| 222 |
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#define MATCH_SFENCE_VM 0x10100073
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| 223 |
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#define MASK_SFENCE_VM 0xfff07fff
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| 224 |
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#define MATCH_WFI 0x10200073
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| 225 |
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#define MASK_WFI 0xffffffff
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| 226 |
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#define MATCH_MRTH 0x30600073
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| 227 |
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#define MASK_MRTH 0xffffffff
|
| 228 |
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#define MATCH_MRTS 0x30500073
|
| 229 |
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#define MASK_MRTS 0xffffffff
|
| 230 |
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#define MATCH_HRTS 0x20500073
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| 231 |
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#define MASK_HRTS 0xffffffff
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| 232 |
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#define MATCH_CSRRW 0x1073
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| 233 |
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#define MASK_CSRRW 0x707f
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| 234 |
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#define MATCH_CSRRS 0x2073
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| 235 |
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#define MASK_CSRRS 0x707f
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| 236 |
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#define MATCH_CSRRC 0x3073
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| 237 |
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#define MASK_CSRRC 0x707f
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| 238 |
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#define MATCH_CSRRWI 0x5073
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| 239 |
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#define MASK_CSRRWI 0x707f
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| 240 |
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#define MATCH_CSRRSI 0x6073
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| 241 |
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#define MASK_CSRRSI 0x707f
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| 242 |
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#define MATCH_CSRRCI 0x7073
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| 243 |
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#define MASK_CSRRCI 0x707f
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| 244 |
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#define MATCH_FADD_S 0x53
|
| 245 |
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#define MASK_FADD_S 0xfe00007f
|
| 246 |
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#define MATCH_FSUB_S 0x8000053
|
| 247 |
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#define MASK_FSUB_S 0xfe00007f
|
| 248 |
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#define MATCH_FMUL_S 0x10000053
|
| 249 |
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#define MASK_FMUL_S 0xfe00007f
|
| 250 |
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#define MATCH_FDIV_S 0x18000053
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| 251 |
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#define MASK_FDIV_S 0xfe00007f
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| 252 |
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#define MATCH_FSGNJ_S 0x20000053
|
| 253 |
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#define MASK_FSGNJ_S 0xfe00707f
|
| 254 |
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#define MATCH_FSGNJN_S 0x20001053
|
| 255 |
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#define MASK_FSGNJN_S 0xfe00707f
|
| 256 |
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#define MATCH_FSGNJX_S 0x20002053
|
| 257 |
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#define MASK_FSGNJX_S 0xfe00707f
|
| 258 |
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#define MATCH_FMIN_S 0x28000053
|
| 259 |
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#define MASK_FMIN_S 0xfe00707f
|
| 260 |
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#define MATCH_FMAX_S 0x28001053
|
| 261 |
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#define MASK_FMAX_S 0xfe00707f
|
| 262 |
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#define MATCH_FSQRT_S 0x58000053
|
| 263 |
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#define MASK_FSQRT_S 0xfff0007f
|
| 264 |
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#define MATCH_FADD_D 0x2000053
|
| 265 |
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#define MASK_FADD_D 0xfe00007f
|
| 266 |
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#define MATCH_FSUB_D 0xa000053
|
| 267 |
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#define MASK_FSUB_D 0xfe00007f
|
| 268 |
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#define MATCH_FMUL_D 0x12000053
|
| 269 |
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#define MASK_FMUL_D 0xfe00007f
|
| 270 |
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#define MATCH_FDIV_D 0x1a000053
|
| 271 |
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#define MASK_FDIV_D 0xfe00007f
|
| 272 |
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#define MATCH_FSGNJ_D 0x22000053
|
| 273 |
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#define MASK_FSGNJ_D 0xfe00707f
|
| 274 |
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#define MATCH_FSGNJN_D 0x22001053
|
| 275 |
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#define MASK_FSGNJN_D 0xfe00707f
|
| 276 |
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#define MATCH_FSGNJX_D 0x22002053
|
| 277 |
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#define MASK_FSGNJX_D 0xfe00707f
|
| 278 |
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#define MATCH_FMIN_D 0x2a000053
|
| 279 |
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#define MASK_FMIN_D 0xfe00707f
|
| 280 |
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#define MATCH_FMAX_D 0x2a001053
|
| 281 |
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#define MASK_FMAX_D 0xfe00707f
|
| 282 |
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#define MATCH_FCVT_S_D 0x40100053
|
| 283 |
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#define MASK_FCVT_S_D 0xfff0007f
|
| 284 |
|
|
#define MATCH_FCVT_D_S 0x42000053
|
| 285 |
|
|
#define MASK_FCVT_D_S 0xfff0007f
|
| 286 |
|
|
#define MATCH_FSQRT_D 0x5a000053
|
| 287 |
|
|
#define MASK_FSQRT_D 0xfff0007f
|
| 288 |
|
|
#define MATCH_FLE_S 0xa0000053
|
| 289 |
|
|
#define MASK_FLE_S 0xfe00707f
|
| 290 |
|
|
#define MATCH_FLT_S 0xa0001053
|
| 291 |
|
|
#define MASK_FLT_S 0xfe00707f
|
| 292 |
|
|
#define MATCH_FEQ_S 0xa0002053
|
| 293 |
|
|
#define MASK_FEQ_S 0xfe00707f
|
| 294 |
|
|
#define MATCH_FLE_D 0xa2000053
|
| 295 |
|
|
#define MASK_FLE_D 0xfe00707f
|
| 296 |
|
|
#define MATCH_FLT_D 0xa2001053
|
| 297 |
|
|
#define MASK_FLT_D 0xfe00707f
|
| 298 |
|
|
#define MATCH_FEQ_D 0xa2002053
|
| 299 |
|
|
#define MASK_FEQ_D 0xfe00707f
|
| 300 |
|
|
#define MATCH_FCVT_W_S 0xc0000053
|
| 301 |
|
|
#define MASK_FCVT_W_S 0xfff0007f
|
| 302 |
|
|
#define MATCH_FCVT_WU_S 0xc0100053
|
| 303 |
|
|
#define MASK_FCVT_WU_S 0xfff0007f
|
| 304 |
|
|
#define MATCH_FCVT_L_S 0xc0200053
|
| 305 |
|
|
#define MASK_FCVT_L_S 0xfff0007f
|
| 306 |
|
|
#define MATCH_FCVT_LU_S 0xc0300053
|
| 307 |
|
|
#define MASK_FCVT_LU_S 0xfff0007f
|
| 308 |
|
|
#define MATCH_FMV_X_S 0xe0000053
|
| 309 |
|
|
#define MASK_FMV_X_S 0xfff0707f
|
| 310 |
|
|
#define MATCH_FCLASS_S 0xe0001053
|
| 311 |
|
|
#define MASK_FCLASS_S 0xfff0707f
|
| 312 |
|
|
#define MATCH_FCVT_W_D 0xc2000053
|
| 313 |
|
|
#define MASK_FCVT_W_D 0xfff0007f
|
| 314 |
|
|
#define MATCH_FCVT_WU_D 0xc2100053
|
| 315 |
|
|
#define MASK_FCVT_WU_D 0xfff0007f
|
| 316 |
|
|
#define MATCH_FCVT_L_D 0xc2200053
|
| 317 |
|
|
#define MASK_FCVT_L_D 0xfff0007f
|
| 318 |
|
|
#define MATCH_FCVT_LU_D 0xc2300053
|
| 319 |
|
|
#define MASK_FCVT_LU_D 0xfff0007f
|
| 320 |
|
|
#define MATCH_FMV_X_D 0xe2000053
|
| 321 |
|
|
#define MASK_FMV_X_D 0xfff0707f
|
| 322 |
|
|
#define MATCH_FCLASS_D 0xe2001053
|
| 323 |
|
|
#define MASK_FCLASS_D 0xfff0707f
|
| 324 |
|
|
#define MATCH_FCVT_S_W 0xd0000053
|
| 325 |
|
|
#define MASK_FCVT_S_W 0xfff0007f
|
| 326 |
|
|
#define MATCH_FCVT_S_WU 0xd0100053
|
| 327 |
|
|
#define MASK_FCVT_S_WU 0xfff0007f
|
| 328 |
|
|
#define MATCH_FCVT_S_L 0xd0200053
|
| 329 |
|
|
#define MASK_FCVT_S_L 0xfff0007f
|
| 330 |
|
|
#define MATCH_FCVT_S_LU 0xd0300053
|
| 331 |
|
|
#define MASK_FCVT_S_LU 0xfff0007f
|
| 332 |
|
|
#define MATCH_FMV_S_X 0xf0000053
|
| 333 |
|
|
#define MASK_FMV_S_X 0xfff0707f
|
| 334 |
|
|
#define MATCH_FCVT_D_W 0xd2000053
|
| 335 |
|
|
#define MASK_FCVT_D_W 0xfff0007f
|
| 336 |
|
|
#define MATCH_FCVT_D_WU 0xd2100053
|
| 337 |
|
|
#define MASK_FCVT_D_WU 0xfff0007f
|
| 338 |
|
|
#define MATCH_FCVT_D_L 0xd2200053
|
| 339 |
|
|
#define MASK_FCVT_D_L 0xfff0007f
|
| 340 |
|
|
#define MATCH_FCVT_D_LU 0xd2300053
|
| 341 |
|
|
#define MASK_FCVT_D_LU 0xfff0007f
|
| 342 |
|
|
#define MATCH_FMV_D_X 0xf2000053
|
| 343 |
|
|
#define MASK_FMV_D_X 0xfff0707f
|
| 344 |
|
|
#define MATCH_FLW 0x2007
|
| 345 |
|
|
#define MASK_FLW 0x707f
|
| 346 |
|
|
#define MATCH_FLD 0x3007
|
| 347 |
|
|
#define MASK_FLD 0x707f
|
| 348 |
|
|
#define MATCH_FSW 0x2027
|
| 349 |
|
|
#define MASK_FSW 0x707f
|
| 350 |
|
|
#define MATCH_FSD 0x3027
|
| 351 |
|
|
#define MASK_FSD 0x707f
|
| 352 |
|
|
#define MATCH_FMADD_S 0x43
|
| 353 |
|
|
#define MASK_FMADD_S 0x600007f
|
| 354 |
|
|
#define MATCH_FMSUB_S 0x47
|
| 355 |
|
|
#define MASK_FMSUB_S 0x600007f
|
| 356 |
|
|
#define MATCH_FNMSUB_S 0x4b
|
| 357 |
|
|
#define MASK_FNMSUB_S 0x600007f
|
| 358 |
|
|
#define MATCH_FNMADD_S 0x4f
|
| 359 |
|
|
#define MASK_FNMADD_S 0x600007f
|
| 360 |
|
|
#define MATCH_FMADD_D 0x2000043
|
| 361 |
|
|
#define MASK_FMADD_D 0x600007f
|
| 362 |
|
|
#define MATCH_FMSUB_D 0x2000047
|
| 363 |
|
|
#define MASK_FMSUB_D 0x600007f
|
| 364 |
|
|
#define MATCH_FNMSUB_D 0x200004b
|
| 365 |
|
|
#define MASK_FNMSUB_D 0x600007f
|
| 366 |
|
|
#define MATCH_FNMADD_D 0x200004f
|
| 367 |
|
|
#define MASK_FNMADD_D 0x600007f
|
| 368 |
|
|
#define MATCH_C_ADDI4SPN 0x0
|
| 369 |
|
|
#define MASK_C_ADDI4SPN 0xe003
|
| 370 |
|
|
#define MATCH_C_FLD 0x2000
|
| 371 |
|
|
#define MASK_C_FLD 0xe003
|
| 372 |
|
|
#define MATCH_C_LW 0x4000
|
| 373 |
|
|
#define MASK_C_LW 0xe003
|
| 374 |
|
|
#define MATCH_C_FLW 0x6000
|
| 375 |
|
|
#define MASK_C_FLW 0xe003
|
| 376 |
|
|
#define MATCH_C_FSD 0xa000
|
| 377 |
|
|
#define MASK_C_FSD 0xe003
|
| 378 |
|
|
#define MATCH_C_SW 0xc000
|
| 379 |
|
|
#define MASK_C_SW 0xe003
|
| 380 |
|
|
#define MATCH_C_FSW 0xe000
|
| 381 |
|
|
#define MASK_C_FSW 0xe003
|
| 382 |
|
|
#define MATCH_C_ADDI 0x1
|
| 383 |
|
|
#define MASK_C_ADDI 0xe003
|
| 384 |
|
|
#define MATCH_C_JAL 0x2001
|
| 385 |
|
|
#define MASK_C_JAL 0xe003
|
| 386 |
|
|
#define MATCH_C_LI 0x4001
|
| 387 |
|
|
#define MASK_C_LI 0xe003
|
| 388 |
|
|
#define MATCH_C_LUI 0x6001
|
| 389 |
|
|
#define MASK_C_LUI 0xe003
|
| 390 |
|
|
#define MATCH_C_SRLI 0x8001
|
| 391 |
|
|
#define MASK_C_SRLI 0xec03
|
| 392 |
|
|
#define MATCH_C_SRAI 0x8401
|
| 393 |
|
|
#define MASK_C_SRAI 0xec03
|
| 394 |
|
|
#define MATCH_C_ANDI 0x8801
|
| 395 |
|
|
#define MASK_C_ANDI 0xec03
|
| 396 |
|
|
#define MATCH_C_SUB 0x8c01
|
| 397 |
|
|
#define MASK_C_SUB 0xfc63
|
| 398 |
|
|
#define MATCH_C_XOR 0x8c21
|
| 399 |
|
|
#define MASK_C_XOR 0xfc63
|
| 400 |
|
|
#define MATCH_C_OR 0x8c41
|
| 401 |
|
|
#define MASK_C_OR 0xfc63
|
| 402 |
|
|
#define MATCH_C_AND 0x8c61
|
| 403 |
|
|
#define MASK_C_AND 0xfc63
|
| 404 |
|
|
#define MATCH_C_SUBW 0x9c01
|
| 405 |
|
|
#define MASK_C_SUBW 0xfc63
|
| 406 |
|
|
#define MATCH_C_ADDW 0x9c21
|
| 407 |
|
|
#define MASK_C_ADDW 0xfc63
|
| 408 |
|
|
#define MATCH_C_J 0xa001
|
| 409 |
|
|
#define MASK_C_J 0xe003
|
| 410 |
|
|
#define MATCH_C_BEQZ 0xc001
|
| 411 |
|
|
#define MASK_C_BEQZ 0xe003
|
| 412 |
|
|
#define MATCH_C_BNEZ 0xe001
|
| 413 |
|
|
#define MASK_C_BNEZ 0xe003
|
| 414 |
|
|
#define MATCH_C_SLLI 0x2
|
| 415 |
|
|
#define MASK_C_SLLI 0xe003
|
| 416 |
|
|
#define MATCH_C_FLDSP 0x2002
|
| 417 |
|
|
#define MASK_C_FLDSP 0xe003
|
| 418 |
|
|
#define MATCH_C_LWSP 0x4002
|
| 419 |
|
|
#define MASK_C_LWSP 0xe003
|
| 420 |
|
|
#define MATCH_C_FLWSP 0x6002
|
| 421 |
|
|
#define MASK_C_FLWSP 0xe003
|
| 422 |
|
|
#define MATCH_C_MV 0x8002
|
| 423 |
|
|
#define MASK_C_MV 0xf003
|
| 424 |
|
|
#define MATCH_C_ADD 0x9002
|
| 425 |
|
|
#define MASK_C_ADD 0xf003
|
| 426 |
|
|
#define MATCH_C_FSDSP 0xa002
|
| 427 |
|
|
#define MASK_C_FSDSP 0xe003
|
| 428 |
|
|
#define MATCH_C_SWSP 0xc002
|
| 429 |
|
|
#define MASK_C_SWSP 0xe003
|
| 430 |
|
|
#define MATCH_C_FSWSP 0xe002
|
| 431 |
|
|
#define MASK_C_FSWSP 0xe003
|
| 432 |
|
|
#define MATCH_C_NOP 0x1
|
| 433 |
|
|
#define MASK_C_NOP 0xffff
|
| 434 |
|
|
#define MATCH_C_ADDI16SP 0x6101
|
| 435 |
|
|
#define MASK_C_ADDI16SP 0xef83
|
| 436 |
|
|
#define MATCH_C_JR 0x8002
|
| 437 |
|
|
#define MASK_C_JR 0xf07f
|
| 438 |
|
|
#define MATCH_C_JALR 0x9002
|
| 439 |
|
|
#define MASK_C_JALR 0xf07f
|
| 440 |
|
|
#define MATCH_C_EBREAK 0x9002
|
| 441 |
|
|
#define MASK_C_EBREAK 0xffff
|
| 442 |
|
|
#define MATCH_C_LD 0x6000
|
| 443 |
|
|
#define MASK_C_LD 0xe003
|
| 444 |
|
|
#define MATCH_C_SD 0xe000
|
| 445 |
|
|
#define MASK_C_SD 0xe003
|
| 446 |
|
|
#define MATCH_C_ADDIW 0x2001
|
| 447 |
|
|
#define MASK_C_ADDIW 0xe003
|
| 448 |
|
|
#define MATCH_C_LDSP 0x6002
|
| 449 |
|
|
#define MASK_C_LDSP 0xe003
|
| 450 |
|
|
#define MATCH_C_SDSP 0xe002
|
| 451 |
|
|
#define MASK_C_SDSP 0xe003
|
| 452 |
|
|
#define MATCH_VLD 0x600205b
|
| 453 |
|
|
#define MASK_VLD 0xfff0707f
|
| 454 |
|
|
#define MATCH_VLW 0x400205b
|
| 455 |
|
|
#define MASK_VLW 0xfff0707f
|
| 456 |
|
|
#define MATCH_VLWU 0xc00205b
|
| 457 |
|
|
#define MASK_VLWU 0xfff0707f
|
| 458 |
|
|
#define MATCH_VLH 0x200205b
|
| 459 |
|
|
#define MASK_VLH 0xfff0707f
|
| 460 |
|
|
#define MATCH_VLHU 0xa00205b
|
| 461 |
|
|
#define MASK_VLHU 0xfff0707f
|
| 462 |
|
|
#define MATCH_VLB 0x205b
|
| 463 |
|
|
#define MASK_VLB 0xfff0707f
|
| 464 |
|
|
#define MATCH_VLBU 0x800205b
|
| 465 |
|
|
#define MASK_VLBU 0xfff0707f
|
| 466 |
|
|
#define MATCH_VFLD 0x1600205b
|
| 467 |
|
|
#define MASK_VFLD 0xfff0707f
|
| 468 |
|
|
#define MATCH_VFLW 0x1400205b
|
| 469 |
|
|
#define MASK_VFLW 0xfff0707f
|
| 470 |
|
|
#define MATCH_VLSTD 0x600305b
|
| 471 |
|
|
#define MASK_VLSTD 0xfe00707f
|
| 472 |
|
|
#define MATCH_VLSTW 0x400305b
|
| 473 |
|
|
#define MASK_VLSTW 0xfe00707f
|
| 474 |
|
|
#define MATCH_VLSTWU 0xc00305b
|
| 475 |
|
|
#define MASK_VLSTWU 0xfe00707f
|
| 476 |
|
|
#define MATCH_VLSTH 0x200305b
|
| 477 |
|
|
#define MASK_VLSTH 0xfe00707f
|
| 478 |
|
|
#define MATCH_VLSTHU 0xa00305b
|
| 479 |
|
|
#define MASK_VLSTHU 0xfe00707f
|
| 480 |
|
|
#define MATCH_VLSTB 0x305b
|
| 481 |
|
|
#define MASK_VLSTB 0xfe00707f
|
| 482 |
|
|
#define MATCH_VLSTBU 0x800305b
|
| 483 |
|
|
#define MASK_VLSTBU 0xfe00707f
|
| 484 |
|
|
#define MATCH_VFLSTD 0x1600305b
|
| 485 |
|
|
#define MASK_VFLSTD 0xfe00707f
|
| 486 |
|
|
#define MATCH_VFLSTW 0x1400305b
|
| 487 |
|
|
#define MASK_VFLSTW 0xfe00707f
|
| 488 |
|
|
#define MATCH_VSD 0x600207b
|
| 489 |
|
|
#define MASK_VSD 0xfff0707f
|
| 490 |
|
|
#define MATCH_VSW 0x400207b
|
| 491 |
|
|
#define MASK_VSW 0xfff0707f
|
| 492 |
|
|
#define MATCH_VSH 0x200207b
|
| 493 |
|
|
#define MASK_VSH 0xfff0707f
|
| 494 |
|
|
#define MATCH_VSB 0x207b
|
| 495 |
|
|
#define MASK_VSB 0xfff0707f
|
| 496 |
|
|
#define MATCH_VFSD 0x1600207b
|
| 497 |
|
|
#define MASK_VFSD 0xfff0707f
|
| 498 |
|
|
#define MATCH_VFSW 0x1400207b
|
| 499 |
|
|
#define MASK_VFSW 0xfff0707f
|
| 500 |
|
|
#define MATCH_VSSTD 0x600307b
|
| 501 |
|
|
#define MASK_VSSTD 0xfe00707f
|
| 502 |
|
|
#define MATCH_VSSTW 0x400307b
|
| 503 |
|
|
#define MASK_VSSTW 0xfe00707f
|
| 504 |
|
|
#define MATCH_VSSTH 0x200307b
|
| 505 |
|
|
#define MASK_VSSTH 0xfe00707f
|
| 506 |
|
|
#define MATCH_VSSTB 0x307b
|
| 507 |
|
|
#define MASK_VSSTB 0xfe00707f
|
| 508 |
|
|
#define MATCH_VFSSTD 0x1600307b
|
| 509 |
|
|
#define MASK_VFSSTD 0xfe00707f
|
| 510 |
|
|
#define MATCH_VFSSTW 0x1400307b
|
| 511 |
|
|
#define MASK_VFSSTW 0xfe00707f
|
| 512 |
|
|
#define MATCH_VSETCFG 0x200b
|
| 513 |
|
|
#define MASK_VSETCFG 0x7fff
|
| 514 |
|
|
#define MATCH_VSETVL 0x600b
|
| 515 |
|
|
#define MASK_VSETVL 0xfff0707f
|
| 516 |
|
|
#define MATCH_VGETCFG 0x400b
|
| 517 |
|
|
#define MASK_VGETCFG 0xfffff07f
|
| 518 |
|
|
#define MATCH_VGETVL 0x200400b
|
| 519 |
|
|
#define MASK_VGETVL 0xfffff07f
|
| 520 |
|
|
#define MATCH_VMVV 0x200002b
|
| 521 |
|
|
#define MASK_VMVV 0xfff0707f
|
| 522 |
|
|
#define MATCH_VMSV 0x200202b
|
| 523 |
|
|
#define MASK_VMSV 0xfff0707f
|
| 524 |
|
|
#define MATCH_VFMVV 0x1000002b
|
| 525 |
|
|
#define MASK_VFMVV 0xfff0707f
|
| 526 |
|
|
#define MATCH_VFMVV 0x1000002b
|
| 527 |
|
|
#define MASK_VFMVV 0xfff0707f
|
| 528 |
|
|
#define MATCH_VFMSV_S 0x1000202b
|
| 529 |
|
|
#define MASK_VFMSV_S 0xfff0707f
|
| 530 |
|
|
#define MATCH_VFMSV_D 0x1200202b
|
| 531 |
|
|
#define MASK_VFMSV_D 0xfff0707f
|
| 532 |
|
|
#define MATCH_VF 0x10202b
|
| 533 |
|
|
#define MASK_VF 0x1f0707f
|
| 534 |
|
|
#define MATCH_VXCPTCAUSE 0x402b
|
| 535 |
|
|
#define MASK_VXCPTCAUSE 0xfffff07f
|
| 536 |
|
|
#define MATCH_VXCPTAUX 0x200402b
|
| 537 |
|
|
#define MASK_VXCPTAUX 0xfffff07f
|
| 538 |
|
|
#define MATCH_VXCPTSAVE 0x302b
|
| 539 |
|
|
#define MASK_VXCPTSAVE 0xfff07fff
|
| 540 |
|
|
#define MATCH_VXCPTRESTORE 0x200302b
|
| 541 |
|
|
#define MASK_VXCPTRESTORE 0xfff07fff
|
| 542 |
|
|
#define MATCH_VXCPTKILL 0x400302b
|
| 543 |
|
|
#define MASK_VXCPTKILL 0xffffffff
|
| 544 |
|
|
#define MATCH_VXCPTEVAC 0x600302b
|
| 545 |
|
|
#define MASK_VXCPTEVAC 0xfff07fff
|
| 546 |
|
|
#define MATCH_VXCPTHOLD 0x800302b
|
| 547 |
|
|
#define MASK_VXCPTHOLD 0xfff07fff
|
| 548 |
|
|
#define MATCH_VENQCMD 0xa00302b
|
| 549 |
|
|
#define MASK_VENQCMD 0xfe007fff
|
| 550 |
|
|
#define MATCH_VENQIMM1 0xc00302b
|
| 551 |
|
|
#define MASK_VENQIMM1 0xfe007fff
|
| 552 |
|
|
#define MATCH_VENQIMM2 0xe00302b
|
| 553 |
|
|
#define MASK_VENQIMM2 0xfe007fff
|
| 554 |
|
|
#define MATCH_VENQCNT 0x1000302b
|
| 555 |
|
|
#define MASK_VENQCNT 0xfe007fff
|
| 556 |
|
|
#define MATCH_VLSEGD 0x600205b
|
| 557 |
|
|
#define MASK_VLSEGD 0x1ff0707f
|
| 558 |
|
|
#define MATCH_VLSEGW 0x400205b
|
| 559 |
|
|
#define MASK_VLSEGW 0x1ff0707f
|
| 560 |
|
|
#define MATCH_VLSEGWU 0xc00205b
|
| 561 |
|
|
#define MASK_VLSEGWU 0x1ff0707f
|
| 562 |
|
|
#define MATCH_VLSEGH 0x200205b
|
| 563 |
|
|
#define MASK_VLSEGH 0x1ff0707f
|
| 564 |
|
|
#define MATCH_VLSEGHU 0xa00205b
|
| 565 |
|
|
#define MASK_VLSEGHU 0x1ff0707f
|
| 566 |
|
|
#define MATCH_VLSEGB 0x205b
|
| 567 |
|
|
#define MASK_VLSEGB 0x1ff0707f
|
| 568 |
|
|
#define MATCH_VLSEGBU 0x800205b
|
| 569 |
|
|
#define MASK_VLSEGBU 0x1ff0707f
|
| 570 |
|
|
#define MATCH_VFLSEGD 0x1600205b
|
| 571 |
|
|
#define MASK_VFLSEGD 0x1ff0707f
|
| 572 |
|
|
#define MATCH_VFLSEGW 0x1400205b
|
| 573 |
|
|
#define MASK_VFLSEGW 0x1ff0707f
|
| 574 |
|
|
#define MATCH_VLSEGSTD 0x600305b
|
| 575 |
|
|
#define MASK_VLSEGSTD 0x1e00707f
|
| 576 |
|
|
#define MATCH_VLSEGSTW 0x400305b
|
| 577 |
|
|
#define MASK_VLSEGSTW 0x1e00707f
|
| 578 |
|
|
#define MATCH_VLSEGSTWU 0xc00305b
|
| 579 |
|
|
#define MASK_VLSEGSTWU 0x1e00707f
|
| 580 |
|
|
#define MATCH_VLSEGSTH 0x200305b
|
| 581 |
|
|
#define MASK_VLSEGSTH 0x1e00707f
|
| 582 |
|
|
#define MATCH_VLSEGSTHU 0xa00305b
|
| 583 |
|
|
#define MASK_VLSEGSTHU 0x1e00707f
|
| 584 |
|
|
#define MATCH_VLSEGSTB 0x305b
|
| 585 |
|
|
#define MASK_VLSEGSTB 0x1e00707f
|
| 586 |
|
|
#define MATCH_VLSEGSTBU 0x800305b
|
| 587 |
|
|
#define MASK_VLSEGSTBU 0x1e00707f
|
| 588 |
|
|
#define MATCH_VFLSEGSTD 0x1600305b
|
| 589 |
|
|
#define MASK_VFLSEGSTD 0x1e00707f
|
| 590 |
|
|
#define MATCH_VFLSEGSTW 0x1400305b
|
| 591 |
|
|
#define MASK_VFLSEGSTW 0x1e00707f
|
| 592 |
|
|
#define MATCH_VSSEGD 0x600207b
|
| 593 |
|
|
#define MASK_VSSEGD 0x1ff0707f
|
| 594 |
|
|
#define MATCH_VSSEGW 0x400207b
|
| 595 |
|
|
#define MASK_VSSEGW 0x1ff0707f
|
| 596 |
|
|
#define MATCH_VSSEGH 0x200207b
|
| 597 |
|
|
#define MASK_VSSEGH 0x1ff0707f
|
| 598 |
|
|
#define MATCH_VSSEGB 0x207b
|
| 599 |
|
|
#define MASK_VSSEGB 0x1ff0707f
|
| 600 |
|
|
#define MATCH_VFSSEGD 0x1600207b
|
| 601 |
|
|
#define MASK_VFSSEGD 0x1ff0707f
|
| 602 |
|
|
#define MATCH_VFSSEGW 0x1400207b
|
| 603 |
|
|
#define MASK_VFSSEGW 0x1ff0707f
|
| 604 |
|
|
#define MATCH_VSSEGSTD 0x600307b
|
| 605 |
|
|
#define MASK_VSSEGSTD 0x1e00707f
|
| 606 |
|
|
#define MATCH_VSSEGSTW 0x400307b
|
| 607 |
|
|
#define MASK_VSSEGSTW 0x1e00707f
|
| 608 |
|
|
#define MATCH_VSSEGSTH 0x200307b
|
| 609 |
|
|
#define MASK_VSSEGSTH 0x1e00707f
|
| 610 |
|
|
#define MATCH_VSSEGSTB 0x307b
|
| 611 |
|
|
#define MASK_VSSEGSTB 0x1e00707f
|
| 612 |
|
|
#define MATCH_VFSSEGSTD 0x1600307b
|
| 613 |
|
|
#define MASK_VFSSEGSTD 0x1e00707f
|
| 614 |
|
|
#define MATCH_VFSSEGSTW 0x1400307b
|
| 615 |
|
|
#define MASK_VFSSEGSTW 0x1e00707f
|
| 616 |
|
|
#define MATCH_STOP 0x5077
|
| 617 |
|
|
#define MASK_STOP 0xffffffff
|
| 618 |
|
|
#define MATCH_UTIDX 0x6077
|
| 619 |
|
|
#define MASK_UTIDX 0xfffff07f
|
| 620 |
|
|
#define MATCH_MOVZ 0x7077
|
| 621 |
|
|
#define MASK_MOVZ 0xfe00707f
|
| 622 |
|
|
#define MATCH_MOVN 0x2007077
|
| 623 |
|
|
#define MASK_MOVN 0xfe00707f
|
| 624 |
|
|
#define MATCH_FMOVZ 0x4007077
|
| 625 |
|
|
#define MASK_FMOVZ 0xfe00707f
|
| 626 |
|
|
#define MATCH_FMOVN 0x6007077
|
| 627 |
|
|
#define MASK_FMOVN 0xfe00707f
|
| 628 |
|
|
#define MATCH_FADD_H 0x4000053
|
| 629 |
|
|
#define MASK_FADD_H 0xfe00007f
|
| 630 |
|
|
#define MATCH_FSUB_H 0xc000053
|
| 631 |
|
|
#define MASK_FSUB_H 0xfe00007f
|
| 632 |
|
|
#define MATCH_FMUL_H 0x14000053
|
| 633 |
|
|
#define MASK_FMUL_H 0xfe00007f
|
| 634 |
|
|
#define MATCH_FDIV_H 0x1c000053
|
| 635 |
|
|
#define MASK_FDIV_H 0xfe00007f
|
| 636 |
|
|
#define MATCH_FSQRT_H 0x24000053
|
| 637 |
|
|
#define MASK_FSQRT_H 0xfff0007f
|
| 638 |
|
|
#define MATCH_FSGNJ_H 0x2c000053
|
| 639 |
|
|
#define MASK_FSGNJ_H 0xfe00707f
|
| 640 |
|
|
#define MATCH_FSGNJN_H 0x34000053
|
| 641 |
|
|
#define MASK_FSGNJN_H 0xfe00707f
|
| 642 |
|
|
#define MATCH_FSGNJX_H 0x3c000053
|
| 643 |
|
|
#define MASK_FSGNJX_H 0xfe00707f
|
| 644 |
|
|
#define MATCH_FCVT_H_L 0x64000053
|
| 645 |
|
|
#define MASK_FCVT_H_L 0xfff0007f
|
| 646 |
|
|
#define MATCH_FCVT_H_LU 0x6c000053
|
| 647 |
|
|
#define MASK_FCVT_H_LU 0xfff0007f
|
| 648 |
|
|
#define MATCH_FCVT_H_W 0x74000053
|
| 649 |
|
|
#define MASK_FCVT_H_W 0xfff0007f
|
| 650 |
|
|
#define MATCH_FCVT_H_WU 0x7c000053
|
| 651 |
|
|
#define MASK_FCVT_H_WU 0xfff0007f
|
| 652 |
|
|
#define MATCH_FCVT_L_H 0x44000053
|
| 653 |
|
|
#define MASK_FCVT_L_H 0xfff0007f
|
| 654 |
|
|
#define MATCH_FCVT_LU_H 0x4c000053
|
| 655 |
|
|
#define MASK_FCVT_LU_H 0xfff0007f
|
| 656 |
|
|
#define MATCH_FCVT_W_H 0x54000053
|
| 657 |
|
|
#define MASK_FCVT_W_H 0xfff0007f
|
| 658 |
|
|
#define MATCH_FCVT_WU_H 0x5c000053
|
| 659 |
|
|
#define MASK_FCVT_WU_H 0xfff0007f
|
| 660 |
|
|
#define MATCH_FCVT_S_H 0x84000053
|
| 661 |
|
|
#define MASK_FCVT_S_H 0xfff0007f
|
| 662 |
|
|
#define MATCH_FCVT_H_S 0x90000053
|
| 663 |
|
|
#define MASK_FCVT_H_S 0xfff0007f
|
| 664 |
|
|
#define MATCH_FCVT_D_H 0x8c000053
|
| 665 |
|
|
#define MASK_FCVT_D_H 0xfff0007f
|
| 666 |
|
|
#define MATCH_FCVT_H_D 0x92000053
|
| 667 |
|
|
#define MASK_FCVT_H_D 0xfff0007f
|
| 668 |
|
|
#define MATCH_FEQ_H 0xac000053
|
| 669 |
|
|
#define MASK_FEQ_H 0xfe00707f
|
| 670 |
|
|
#define MATCH_FLT_H 0xb4000053
|
| 671 |
|
|
#define MASK_FLT_H 0xfe00707f
|
| 672 |
|
|
#define MATCH_FLE_H 0xbc000053
|
| 673 |
|
|
#define MASK_FLE_H 0xfe00707f
|
| 674 |
|
|
#define MATCH_FMIN_H 0xc4000053
|
| 675 |
|
|
#define MASK_FMIN_H 0xfe00707f
|
| 676 |
|
|
#define MATCH_FMAX_H 0xcc000053
|
| 677 |
|
|
#define MASK_FMAX_H 0xfe00707f
|
| 678 |
|
|
#define MATCH_FMV_X_H 0xe4000053
|
| 679 |
|
|
#define MASK_FMV_X_H 0xfff0707f
|
| 680 |
|
|
#define MATCH_FMV_H_X 0xf4000053
|
| 681 |
|
|
#define MASK_FMV_H_X 0xfff0707f
|
| 682 |
|
|
#define MATCH_FLH 0x1007
|
| 683 |
|
|
#define MASK_FLH 0x707f
|
| 684 |
|
|
#define MATCH_FSH 0x1027
|
| 685 |
|
|
#define MASK_FSH 0x707f
|
| 686 |
|
|
#define MATCH_FMADD_H 0x4000043
|
| 687 |
|
|
#define MASK_FMADD_H 0x600007f
|
| 688 |
|
|
#define MATCH_FMSUB_H 0x4000047
|
| 689 |
|
|
#define MASK_FMSUB_H 0x600007f
|
| 690 |
|
|
#define MATCH_FNMSUB_H 0x400004b
|
| 691 |
|
|
#define MASK_FNMSUB_H 0x600007f
|
| 692 |
|
|
#define MATCH_FNMADD_H 0x400004f
|
| 693 |
|
|
#define MASK_FNMADD_H 0x600007f
|
| 694 |
|
|
#define MATCH_CUSTOM0 0xb
|
| 695 |
|
|
#define MASK_CUSTOM0 0x707f
|
| 696 |
|
|
#define MATCH_CUSTOM0_RS1 0x200b
|
| 697 |
|
|
#define MASK_CUSTOM0_RS1 0x707f
|
| 698 |
|
|
#define MATCH_CUSTOM0_RS1_RS2 0x300b
|
| 699 |
|
|
#define MASK_CUSTOM0_RS1_RS2 0x707f
|
| 700 |
|
|
#define MATCH_CUSTOM0_RD 0x400b
|
| 701 |
|
|
#define MASK_CUSTOM0_RD 0x707f
|
| 702 |
|
|
#define MATCH_CUSTOM0_RD_RS1 0x600b
|
| 703 |
|
|
#define MASK_CUSTOM0_RD_RS1 0x707f
|
| 704 |
|
|
#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
|
| 705 |
|
|
#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
|
| 706 |
|
|
#define MATCH_CUSTOM1 0x2b
|
| 707 |
|
|
#define MASK_CUSTOM1 0x707f
|
| 708 |
|
|
#define MATCH_CUSTOM1_RS1 0x202b
|
| 709 |
|
|
#define MASK_CUSTOM1_RS1 0x707f
|
| 710 |
|
|
#define MATCH_CUSTOM1_RS1_RS2 0x302b
|
| 711 |
|
|
#define MASK_CUSTOM1_RS1_RS2 0x707f
|
| 712 |
|
|
#define MATCH_CUSTOM1_RD 0x402b
|
| 713 |
|
|
#define MASK_CUSTOM1_RD 0x707f
|
| 714 |
|
|
#define MATCH_CUSTOM1_RD_RS1 0x602b
|
| 715 |
|
|
#define MASK_CUSTOM1_RD_RS1 0x707f
|
| 716 |
|
|
#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
|
| 717 |
|
|
#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
|
| 718 |
|
|
#define MATCH_CUSTOM2 0x5b
|
| 719 |
|
|
#define MASK_CUSTOM2 0x707f
|
| 720 |
|
|
#define MATCH_CUSTOM2_RS1 0x205b
|
| 721 |
|
|
#define MASK_CUSTOM2_RS1 0x707f
|
| 722 |
|
|
#define MATCH_CUSTOM2_RS1_RS2 0x305b
|
| 723 |
|
|
#define MASK_CUSTOM2_RS1_RS2 0x707f
|
| 724 |
|
|
#define MATCH_CUSTOM2_RD 0x405b
|
| 725 |
|
|
#define MASK_CUSTOM2_RD 0x707f
|
| 726 |
|
|
#define MATCH_CUSTOM2_RD_RS1 0x605b
|
| 727 |
|
|
#define MASK_CUSTOM2_RD_RS1 0x707f
|
| 728 |
|
|
#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
|
| 729 |
|
|
#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
|
| 730 |
|
|
#define MATCH_CUSTOM3 0x7b
|
| 731 |
|
|
#define MASK_CUSTOM3 0x707f
|
| 732 |
|
|
#define MATCH_CUSTOM3_RS1 0x207b
|
| 733 |
|
|
#define MASK_CUSTOM3_RS1 0x707f
|
| 734 |
|
|
#define MATCH_CUSTOM3_RS1_RS2 0x307b
|
| 735 |
|
|
#define MASK_CUSTOM3_RS1_RS2 0x707f
|
| 736 |
|
|
#define MATCH_CUSTOM3_RD 0x407b
|
| 737 |
|
|
#define MASK_CUSTOM3_RD 0x707f
|
| 738 |
|
|
#define MATCH_CUSTOM3_RD_RS1 0x607b
|
| 739 |
|
|
#define MASK_CUSTOM3_RD_RS1 0x707f
|
| 740 |
|
|
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
|
| 741 |
|
|
#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
|
| 742 |
|
|
#define CSR_FFLAGS 0x1
|
| 743 |
|
|
#define CSR_FRM 0x2
|
| 744 |
|
|
#define CSR_FCSR 0x3
|
| 745 |
|
|
#define CSR_CYCLE 0xc00
|
| 746 |
|
|
#define CSR_TIME 0xc01
|
| 747 |
|
|
#define CSR_INSTRET 0xc02
|
| 748 |
|
|
#define CSR_STATS 0xc0
|
| 749 |
|
|
#define CSR_UARCH0 0xcc0
|
| 750 |
|
|
#define CSR_UARCH1 0xcc1
|
| 751 |
|
|
#define CSR_UARCH2 0xcc2
|
| 752 |
|
|
#define CSR_UARCH3 0xcc3
|
| 753 |
|
|
#define CSR_UARCH4 0xcc4
|
| 754 |
|
|
#define CSR_UARCH5 0xcc5
|
| 755 |
|
|
#define CSR_UARCH6 0xcc6
|
| 756 |
|
|
#define CSR_UARCH7 0xcc7
|
| 757 |
|
|
#define CSR_UARCH8 0xcc8
|
| 758 |
|
|
#define CSR_UARCH9 0xcc9
|
| 759 |
|
|
#define CSR_UARCH10 0xcca
|
| 760 |
|
|
#define CSR_UARCH11 0xccb
|
| 761 |
|
|
#define CSR_UARCH12 0xccc
|
| 762 |
|
|
#define CSR_UARCH13 0xccd
|
| 763 |
|
|
#define CSR_UARCH14 0xcce
|
| 764 |
|
|
#define CSR_UARCH15 0xccf
|
| 765 |
|
|
#define CSR_SSTATUS 0x100
|
| 766 |
|
|
#define CSR_STVEC 0x101
|
| 767 |
|
|
#define CSR_SIE 0x104
|
| 768 |
|
|
#define CSR_SSCRATCH 0x140
|
| 769 |
|
|
#define CSR_SEPC 0x141
|
| 770 |
|
|
#define CSR_SIP 0x144
|
| 771 |
|
|
#define CSR_SPTBR 0x180
|
| 772 |
|
|
#define CSR_SASID 0x181
|
| 773 |
|
|
#define CSR_CYCLEW 0x900
|
| 774 |
|
|
#define CSR_TIMEW 0x901
|
| 775 |
|
|
#define CSR_INSTRETW 0x902
|
| 776 |
|
|
#define CSR_STIME 0xd01
|
| 777 |
|
|
#define CSR_SCAUSE 0xd42
|
| 778 |
|
|
#define CSR_SBADADDR 0xd43
|
| 779 |
|
|
#define CSR_STIMEW 0xa01
|
| 780 |
|
|
#define CSR_MSTATUS 0x300
|
| 781 |
|
|
#define CSR_MTVEC 0x301
|
| 782 |
|
|
#define CSR_MTDELEG 0x302
|
| 783 |
|
|
#define CSR_MIE 0x304
|
| 784 |
|
|
#define CSR_MTIMECMP 0x321
|
| 785 |
|
|
#define CSR_MSCRATCH 0x340
|
| 786 |
|
|
#define CSR_MEPC 0x341
|
| 787 |
|
|
#define CSR_MCAUSE 0x342
|
| 788 |
|
|
#define CSR_MBADADDR 0x343
|
| 789 |
|
|
#define CSR_MIP 0x344
|
| 790 |
|
|
#define CSR_MTIME 0x701
|
| 791 |
|
|
#define CSR_MCPUID 0xf00
|
| 792 |
|
|
#define CSR_MIMPID 0xf01
|
| 793 |
|
|
#define CSR_MHARTID 0xf10
|
| 794 |
|
|
#define CSR_MTOHOST 0x780
|
| 795 |
|
|
#define CSR_MFROMHOST 0x781
|
| 796 |
|
|
#define CSR_MRESET 0x782
|
| 797 |
|
|
#define CSR_MIPI 0x783
|
| 798 |
|
|
#define CSR_MIOBASE 0x784
|
| 799 |
|
|
#define CSR_CYCLEH 0xc80
|
| 800 |
|
|
#define CSR_TIMEH 0xc81
|
| 801 |
|
|
#define CSR_INSTRETH 0xc82
|
| 802 |
|
|
#define CSR_CYCLEHW 0x980
|
| 803 |
|
|
#define CSR_TIMEHW 0x981
|
| 804 |
|
|
#define CSR_INSTRETHW 0x982
|
| 805 |
|
|
#define CSR_STIMEH 0xd81
|
| 806 |
|
|
#define CSR_STIMEHW 0xa81
|
| 807 |
|
|
#define CSR_MTIMECMPH 0x361
|
| 808 |
|
|
#define CSR_MTIMEH 0x741
|
| 809 |
|
|
#define CAUSE_MISALIGNED_FETCH 0x0
|
| 810 |
|
|
#define CAUSE_FAULT_FETCH 0x1
|
| 811 |
|
|
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
|
| 812 |
|
|
#define CAUSE_BREAKPOINT 0x3
|
| 813 |
|
|
#define CAUSE_MISALIGNED_LOAD 0x4
|
| 814 |
|
|
#define CAUSE_FAULT_LOAD 0x5
|
| 815 |
|
|
#define CAUSE_MISALIGNED_STORE 0x6
|
| 816 |
|
|
#define CAUSE_FAULT_STORE 0x7
|
| 817 |
|
|
#define CAUSE_USER_ECALL 0x8
|
| 818 |
|
|
#define CAUSE_SUPERVISOR_ECALL 0x9
|
| 819 |
|
|
#define CAUSE_HYPERVISOR_ECALL 0xa
|
| 820 |
|
|
#define CAUSE_MACHINE_ECALL 0xb
|
| 821 |
|
|
#endif
|
| 822 |
|
|
#ifdef DECLARE_INSN
|
| 823 |
|
|
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
|
| 824 |
|
|
DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
|
| 825 |
|
|
DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
|
| 826 |
|
|
DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
|
| 827 |
|
|
DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
|
| 828 |
|
|
DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
|
| 829 |
|
|
DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
|
| 830 |
|
|
DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
|
| 831 |
|
|
DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
|
| 832 |
|
|
DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
|
| 833 |
|
|
DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
|
| 834 |
|
|
DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
|
| 835 |
|
|
DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
|
| 836 |
|
|
DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
|
| 837 |
|
|
DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
|
| 838 |
|
|
DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
|
| 839 |
|
|
DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
|
| 840 |
|
|
DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
|
| 841 |
|
|
DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
|
| 842 |
|
|
DECLARE_INSN(eret, MATCH_ERET, MASK_ERET)
|
| 843 |
|
|
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
|
| 844 |
|
|
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
|
| 845 |
|
|
DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
|
| 846 |
|
|
DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
|
| 847 |
|
|
DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
|
| 848 |
|
|
DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
|
| 849 |
|
|
DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
|
| 850 |
|
|
DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
|
| 851 |
|
|
DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
|
| 852 |
|
|
DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
|
| 853 |
|
|
DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
|
| 854 |
|
|
DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
|
| 855 |
|
|
DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
|
| 856 |
|
|
DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
|
| 857 |
|
|
DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
|
| 858 |
|
|
DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
|
| 859 |
|
|
DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
|
| 860 |
|
|
DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
|
| 861 |
|
|
DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
|
| 862 |
|
|
DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
|
| 863 |
|
|
DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
|
| 864 |
|
|
DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
|
| 865 |
|
|
DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
|
| 866 |
|
|
DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
|
| 867 |
|
|
DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
|
| 868 |
|
|
DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
|
| 869 |
|
|
DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
|
| 870 |
|
|
DECLARE_INSN(or, MATCH_OR, MASK_OR)
|
| 871 |
|
|
DECLARE_INSN(and, MATCH_AND, MASK_AND)
|
| 872 |
|
|
DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
|
| 873 |
|
|
DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
|
| 874 |
|
|
DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
|
| 875 |
|
|
DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
|
| 876 |
|
|
DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
|
| 877 |
|
|
DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
|
| 878 |
|
|
DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
|
| 879 |
|
|
DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
|
| 880 |
|
|
DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
|
| 881 |
|
|
DECLARE_INSN(lb, MATCH_LB, MASK_LB)
|
| 882 |
|
|
DECLARE_INSN(lh, MATCH_LH, MASK_LH)
|
| 883 |
|
|
DECLARE_INSN(lw, MATCH_LW, MASK_LW)
|
| 884 |
|
|
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
|
| 885 |
|
|
DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
|
| 886 |
|
|
DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
|
| 887 |
|
|
DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
|
| 888 |
|
|
DECLARE_INSN(sb, MATCH_SB, MASK_SB)
|
| 889 |
|
|
DECLARE_INSN(sh, MATCH_SH, MASK_SH)
|
| 890 |
|
|
DECLARE_INSN(sw, MATCH_SW, MASK_SW)
|
| 891 |
|
|
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
|
| 892 |
|
|
DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
|
| 893 |
|
|
DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
|
| 894 |
|
|
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
|
| 895 |
|
|
DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
|
| 896 |
|
|
DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| 897 |
|
|
DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
|
| 898 |
|
|
DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
|
| 899 |
|
|
DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
|
| 900 |
|
|
DECLARE_INSN(rem, MATCH_REM, MASK_REM)
|
| 901 |
|
|
DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
|
| 902 |
|
|
DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
|
| 903 |
|
|
DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
|
| 904 |
|
|
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
|
| 905 |
|
|
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
|
| 906 |
|
|
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
|
| 907 |
|
|
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
|
| 908 |
|
|
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
|
| 909 |
|
|
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
|
| 910 |
|
|
DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
|
| 911 |
|
|
DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
|
| 912 |
|
|
DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
|
| 913 |
|
|
DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
|
| 914 |
|
|
DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
|
| 915 |
|
|
DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
|
| 916 |
|
|
DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
|
| 917 |
|
|
DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
|
| 918 |
|
|
DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
|
| 919 |
|
|
DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
|
| 920 |
|
|
DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
|
| 921 |
|
|
DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
|
| 922 |
|
|
DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
|
| 923 |
|
|
DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
|
| 924 |
|
|
DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
|
| 925 |
|
|
DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
|
| 926 |
|
|
DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
|
| 927 |
|
|
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
|
| 928 |
|
|
DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
|
| 929 |
|
|
DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
|
| 930 |
|
|
DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
|
| 931 |
|
|
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
|
| 932 |
|
|
DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
|
| 933 |
|
|
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
|
| 934 |
|
|
DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH)
|
| 935 |
|
|
DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
|
| 936 |
|
|
DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS)
|
| 937 |
|
|
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
|
| 938 |
|
|
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
|
| 939 |
|
|
DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
|
| 940 |
|
|
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
|
| 941 |
|
|
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
|
| 942 |
|
|
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
|
| 943 |
|
|
DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
|
| 944 |
|
|
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
|
| 945 |
|
|
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
|
| 946 |
|
|
DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
|
| 947 |
|
|
DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
|
| 948 |
|
|
DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
|
| 949 |
|
|
DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
|
| 950 |
|
|
DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
|
| 951 |
|
|
DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
|
| 952 |
|
|
DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
|
| 953 |
|
|
DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
|
| 954 |
|
|
DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
|
| 955 |
|
|
DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
|
| 956 |
|
|
DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
|
| 957 |
|
|
DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
|
| 958 |
|
|
DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
|
| 959 |
|
|
DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
|
| 960 |
|
|
DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
|
| 961 |
|
|
DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
|
| 962 |
|
|
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
|
| 963 |
|
|
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
|
| 964 |
|
|
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
|
| 965 |
|
|
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
|
| 966 |
|
|
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
|
| 967 |
|
|
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| 968 |
|
|
DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| 969 |
|
|
DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
|
| 970 |
|
|
DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
|
| 971 |
|
|
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
|
| 972 |
|
|
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
|
| 973 |
|
|
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
|
| 974 |
|
|
DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
|
| 975 |
|
|
DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
|
| 976 |
|
|
DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
|
| 977 |
|
|
DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
|
| 978 |
|
|
DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
|
| 979 |
|
|
DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
|
| 980 |
|
|
DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
|
| 981 |
|
|
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
|
| 982 |
|
|
DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
|
| 983 |
|
|
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
|
| 984 |
|
|
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
|
| 985 |
|
|
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
|
| 986 |
|
|
DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
|
| 987 |
|
|
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
|
| 988 |
|
|
DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
|
| 989 |
|
|
DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
|
| 990 |
|
|
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
|
| 991 |
|
|
DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
|
| 992 |
|
|
DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
|
| 993 |
|
|
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
|
| 994 |
|
|
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
|
| 995 |
|
|
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
|
| 996 |
|
|
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
|
| 997 |
|
|
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
|
| 998 |
|
|
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
|
| 999 |
|
|
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
|
| 1000 |
|
|
DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
|
| 1001 |
|
|
DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
|
| 1002 |
|
|
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
|
| 1003 |
|
|
DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
|
| 1004 |
|
|
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
|
| 1005 |
|
|
DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
|
| 1006 |
|
|
DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
|
| 1007 |
|
|
DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
|
| 1008 |
|
|
DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
|
| 1009 |
|
|
DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
|
| 1010 |
|
|
DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
|
| 1011 |
|
|
DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
|
| 1012 |
|
|
DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
|
| 1013 |
|
|
DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
|
| 1014 |
|
|
DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
|
| 1015 |
|
|
DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
|
| 1016 |
|
|
DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
|
| 1017 |
|
|
DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
|
| 1018 |
|
|
DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
|
| 1019 |
|
|
DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
|
| 1020 |
|
|
DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
|
| 1021 |
|
|
DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
|
| 1022 |
|
|
DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
|
| 1023 |
|
|
DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
|
| 1024 |
|
|
DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
|
| 1025 |
|
|
DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
|
| 1026 |
|
|
DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
|
| 1027 |
|
|
DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
|
| 1028 |
|
|
DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
|
| 1029 |
|
|
DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
|
| 1030 |
|
|
DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| 1031 |
|
|
DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
|
| 1032 |
|
|
DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
|
| 1033 |
|
|
DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
|
| 1034 |
|
|
DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
|
| 1035 |
|
|
DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
|
| 1036 |
|
|
DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
|
| 1037 |
|
|
DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
|
| 1038 |
|
|
DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
|
| 1039 |
|
|
DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
|
| 1040 |
|
|
DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
|
| 1041 |
|
|
DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
|
| 1042 |
|
|
DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
|
| 1043 |
|
|
DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
|
| 1044 |
|
|
DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
|
| 1045 |
|
|
DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
|
| 1046 |
|
|
DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| 1047 |
|
|
DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
|
| 1048 |
|
|
DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
|
| 1049 |
|
|
DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
|
| 1050 |
|
|
DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
|
| 1051 |
|
|
DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
|
| 1052 |
|
|
DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
|
| 1053 |
|
|
DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
|
| 1054 |
|
|
DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
|
| 1055 |
|
|
DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
|
| 1056 |
|
|
DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
|
| 1057 |
|
|
DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
|
| 1058 |
|
|
DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
|
| 1059 |
|
|
DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
|
| 1060 |
|
|
DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
|
| 1061 |
|
|
DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
|
| 1062 |
|
|
DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
|
| 1063 |
|
|
DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
|
| 1064 |
|
|
DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
|
| 1065 |
|
|
DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
|
| 1066 |
|
|
DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
|
| 1067 |
|
|
DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
|
| 1068 |
|
|
DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
|
| 1069 |
|
|
DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
|
| 1070 |
|
|
DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
|
| 1071 |
|
|
DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
|
| 1072 |
|
|
DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
|
| 1073 |
|
|
DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
|
| 1074 |
|
|
DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
|
| 1075 |
|
|
DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
|
| 1076 |
|
|
DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
|
| 1077 |
|
|
DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
|
| 1078 |
|
|
DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
|
| 1079 |
|
|
DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
|
| 1080 |
|
|
DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
|
| 1081 |
|
|
DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
|
| 1082 |
|
|
DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
|
| 1083 |
|
|
DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
|
| 1084 |
|
|
DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
|
| 1085 |
|
|
DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
|
| 1086 |
|
|
DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
|
| 1087 |
|
|
DECLARE_INSN(vf, MATCH_VF, MASK_VF)
|
| 1088 |
|
|
DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
|
| 1089 |
|
|
DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
|
| 1090 |
|
|
DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
|
| 1091 |
|
|
DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
|
| 1092 |
|
|
DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
|
| 1093 |
|
|
DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
|
| 1094 |
|
|
DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
|
| 1095 |
|
|
DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
|
| 1096 |
|
|
DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
|
| 1097 |
|
|
DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
|
| 1098 |
|
|
DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
|
| 1099 |
|
|
DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
|
| 1100 |
|
|
DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
|
| 1101 |
|
|
DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
|
| 1102 |
|
|
DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
|
| 1103 |
|
|
DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
|
| 1104 |
|
|
DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
|
| 1105 |
|
|
DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
|
| 1106 |
|
|
DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
|
| 1107 |
|
|
DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
|
| 1108 |
|
|
DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
|
| 1109 |
|
|
DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
|
| 1110 |
|
|
DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
|
| 1111 |
|
|
DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
|
| 1112 |
|
|
DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
|
| 1113 |
|
|
DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
|
| 1114 |
|
|
DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
|
| 1115 |
|
|
DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
|
| 1116 |
|
|
DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
|
| 1117 |
|
|
DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
|
| 1118 |
|
|
DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
|
| 1119 |
|
|
DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
|
| 1120 |
|
|
DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
|
| 1121 |
|
|
DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
|
| 1122 |
|
|
DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
|
| 1123 |
|
|
DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
|
| 1124 |
|
|
DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
|
| 1125 |
|
|
DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
|
| 1126 |
|
|
DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
|
| 1127 |
|
|
DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
|
| 1128 |
|
|
DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
|
| 1129 |
|
|
DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
|
| 1130 |
|
|
DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
|
| 1131 |
|
|
DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
|
| 1132 |
|
|
DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
|
| 1133 |
|
|
DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
|
| 1134 |
|
|
DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
|
| 1135 |
|
|
DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
|
| 1136 |
|
|
DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
|
| 1137 |
|
|
DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
|
| 1138 |
|
|
DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
|
| 1139 |
|
|
DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
|
| 1140 |
|
|
DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
|
| 1141 |
|
|
DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
|
| 1142 |
|
|
DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
|
| 1143 |
|
|
DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
|
| 1144 |
|
|
DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
|
| 1145 |
|
|
DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
|
| 1146 |
|
|
DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
|
| 1147 |
|
|
DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
|
| 1148 |
|
|
DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
|
| 1149 |
|
|
DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
|
| 1150 |
|
|
DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
|
| 1151 |
|
|
DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
|
| 1152 |
|
|
DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
|
| 1153 |
|
|
DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
|
| 1154 |
|
|
DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
|
| 1155 |
|
|
DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
|
| 1156 |
|
|
DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
|
| 1157 |
|
|
DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
|
| 1158 |
|
|
DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
|
| 1159 |
|
|
DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
|
| 1160 |
|
|
DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
|
| 1161 |
|
|
DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
|
| 1162 |
|
|
DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
|
| 1163 |
|
|
DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
|
| 1164 |
|
|
DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
|
| 1165 |
|
|
DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
|
| 1166 |
|
|
DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
|
| 1167 |
|
|
DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
|
| 1168 |
|
|
DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
|
| 1169 |
|
|
DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
|
| 1170 |
|
|
DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
|
| 1171 |
|
|
DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
|
| 1172 |
|
|
DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
|
| 1173 |
|
|
DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
|
| 1174 |
|
|
DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
|
| 1175 |
|
|
DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
|
| 1176 |
|
|
DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
|
| 1177 |
|
|
DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
|
| 1178 |
|
|
DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
|
| 1179 |
|
|
DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
|
| 1180 |
|
|
DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
|
| 1181 |
|
|
DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
|
| 1182 |
|
|
DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
|
| 1183 |
|
|
DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
|
| 1184 |
|
|
DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
|
| 1185 |
|
|
DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
|
| 1186 |
|
|
DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
|
| 1187 |
|
|
DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
|
| 1188 |
|
|
DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
|
| 1189 |
|
|
DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
|
| 1190 |
|
|
DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
|
| 1191 |
|
|
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
|
| 1192 |
|
|
#endif
|
| 1193 |
|
|
#ifdef DECLARE_CSR
|
| 1194 |
|
|
DECLARE_CSR(fflags, CSR_FFLAGS)
|
| 1195 |
|
|
DECLARE_CSR(frm, CSR_FRM)
|
| 1196 |
|
|
DECLARE_CSR(fcsr, CSR_FCSR)
|
| 1197 |
|
|
DECLARE_CSR(cycle, CSR_CYCLE)
|
| 1198 |
|
|
DECLARE_CSR(time, CSR_TIME)
|
| 1199 |
|
|
DECLARE_CSR(instret, CSR_INSTRET)
|
| 1200 |
|
|
DECLARE_CSR(stats, CSR_STATS)
|
| 1201 |
|
|
DECLARE_CSR(uarch0, CSR_UARCH0)
|
| 1202 |
|
|
DECLARE_CSR(uarch1, CSR_UARCH1)
|
| 1203 |
|
|
DECLARE_CSR(uarch2, CSR_UARCH2)
|
| 1204 |
|
|
DECLARE_CSR(uarch3, CSR_UARCH3)
|
| 1205 |
|
|
DECLARE_CSR(uarch4, CSR_UARCH4)
|
| 1206 |
|
|
DECLARE_CSR(uarch5, CSR_UARCH5)
|
| 1207 |
|
|
DECLARE_CSR(uarch6, CSR_UARCH6)
|
| 1208 |
|
|
DECLARE_CSR(uarch7, CSR_UARCH7)
|
| 1209 |
|
|
DECLARE_CSR(uarch8, CSR_UARCH8)
|
| 1210 |
|
|
DECLARE_CSR(uarch9, CSR_UARCH9)
|
| 1211 |
|
|
DECLARE_CSR(uarch10, CSR_UARCH10)
|
| 1212 |
|
|
DECLARE_CSR(uarch11, CSR_UARCH11)
|
| 1213 |
|
|
DECLARE_CSR(uarch12, CSR_UARCH12)
|
| 1214 |
|
|
DECLARE_CSR(uarch13, CSR_UARCH13)
|
| 1215 |
|
|
DECLARE_CSR(uarch14, CSR_UARCH14)
|
| 1216 |
|
|
DECLARE_CSR(uarch15, CSR_UARCH15)
|
| 1217 |
|
|
DECLARE_CSR(sstatus, CSR_SSTATUS)
|
| 1218 |
|
|
DECLARE_CSR(stvec, CSR_STVEC)
|
| 1219 |
|
|
DECLARE_CSR(sie, CSR_SIE)
|
| 1220 |
|
|
DECLARE_CSR(sscratch, CSR_SSCRATCH)
|
| 1221 |
|
|
DECLARE_CSR(sepc, CSR_SEPC)
|
| 1222 |
|
|
DECLARE_CSR(sip, CSR_SIP)
|
| 1223 |
|
|
DECLARE_CSR(sptbr, CSR_SPTBR)
|
| 1224 |
|
|
DECLARE_CSR(sasid, CSR_SASID)
|
| 1225 |
|
|
DECLARE_CSR(cyclew, CSR_CYCLEW)
|
| 1226 |
|
|
DECLARE_CSR(timew, CSR_TIMEW)
|
| 1227 |
|
|
DECLARE_CSR(instretw, CSR_INSTRETW)
|
| 1228 |
|
|
DECLARE_CSR(stime, CSR_STIME)
|
| 1229 |
|
|
DECLARE_CSR(scause, CSR_SCAUSE)
|
| 1230 |
|
|
DECLARE_CSR(sbadaddr, CSR_SBADADDR)
|
| 1231 |
|
|
DECLARE_CSR(stimew, CSR_STIMEW)
|
| 1232 |
|
|
DECLARE_CSR(mstatus, CSR_MSTATUS)
|
| 1233 |
|
|
DECLARE_CSR(mtvec, CSR_MTVEC)
|
| 1234 |
|
|
DECLARE_CSR(mtdeleg, CSR_MTDELEG)
|
| 1235 |
|
|
DECLARE_CSR(mie, CSR_MIE)
|
| 1236 |
|
|
DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
|
| 1237 |
|
|
DECLARE_CSR(mscratch, CSR_MSCRATCH)
|
| 1238 |
|
|
DECLARE_CSR(mepc, CSR_MEPC)
|
| 1239 |
|
|
DECLARE_CSR(mcause, CSR_MCAUSE)
|
| 1240 |
|
|
DECLARE_CSR(mbadaddr, CSR_MBADADDR)
|
| 1241 |
|
|
DECLARE_CSR(mip, CSR_MIP)
|
| 1242 |
|
|
DECLARE_CSR(mtime, CSR_MTIME)
|
| 1243 |
|
|
DECLARE_CSR(mcpuid, CSR_MCPUID)
|
| 1244 |
|
|
DECLARE_CSR(mimpid, CSR_MIMPID)
|
| 1245 |
|
|
DECLARE_CSR(mhartid, CSR_MHARTID)
|
| 1246 |
|
|
DECLARE_CSR(mtohost, CSR_MTOHOST)
|
| 1247 |
|
|
DECLARE_CSR(mfromhost, CSR_MFROMHOST)
|
| 1248 |
|
|
DECLARE_CSR(mreset, CSR_MRESET)
|
| 1249 |
|
|
DECLARE_CSR(mipi, CSR_MIPI)
|
| 1250 |
|
|
DECLARE_CSR(miobase, CSR_MIOBASE)
|
| 1251 |
|
|
DECLARE_CSR(cycleh, CSR_CYCLEH)
|
| 1252 |
|
|
DECLARE_CSR(timeh, CSR_TIMEH)
|
| 1253 |
|
|
DECLARE_CSR(instreth, CSR_INSTRETH)
|
| 1254 |
|
|
DECLARE_CSR(cyclehw, CSR_CYCLEHW)
|
| 1255 |
|
|
DECLARE_CSR(timehw, CSR_TIMEHW)
|
| 1256 |
|
|
DECLARE_CSR(instrethw, CSR_INSTRETHW)
|
| 1257 |
|
|
DECLARE_CSR(stimeh, CSR_STIMEH)
|
| 1258 |
|
|
DECLARE_CSR(stimehw, CSR_STIMEHW)
|
| 1259 |
|
|
DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
|
| 1260 |
|
|
DECLARE_CSR(mtimeh, CSR_MTIMEH)
|
| 1261 |
|
|
#endif
|
| 1262 |
|
|
#ifdef DECLARE_CAUSE
|
| 1263 |
|
|
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
|
| 1264 |
|
|
DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
|
| 1265 |
|
|
DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
|
| 1266 |
|
|
DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
|
| 1267 |
|
|
DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
|
| 1268 |
|
|
DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
|
| 1269 |
|
|
DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
|
| 1270 |
|
|
DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
|
| 1271 |
|
|
DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
|
| 1272 |
|
|
DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
|
| 1273 |
|
|
DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
|
| 1274 |
|
|
DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
|
| 1275 |
|
|
#endif
|
