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serginhofr |
;; Predicate description for RISC-V target.
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;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
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;; Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
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;; Based on MIPS target for GNU compiler.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_predicate "const_arith_operand"
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(and (match_code "const_int")
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(match_test "SMALL_OPERAND (INTVAL (op))")))
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(define_predicate "arith_operand"
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(ior (match_operand 0 "const_arith_operand")
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(match_operand 0 "register_operand")))
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(define_predicate "sle_operand"
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(and (match_code "const_int")
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(match_test "SMALL_OPERAND (INTVAL (op) + 1)")))
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(define_predicate "sleu_operand"
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(and (match_operand 0 "sle_operand")
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(match_test "INTVAL (op) + 1 != 0")))
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(define_predicate "const_0_operand"
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(and (match_code "const_int,const_double,const_vector")
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(match_test "op == CONST0_RTX (GET_MODE (op))")))
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(define_predicate "reg_or_0_operand"
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(ior (match_operand 0 "const_0_operand")
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(match_operand 0 "register_operand")))
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(define_predicate "const_1_operand"
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(and (match_code "const_int,const_double,const_vector")
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(match_test "op == CONST1_RTX (GET_MODE (op))")))
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(define_predicate "reg_or_1_operand"
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(ior (match_operand 0 "const_1_operand")
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(match_operand 0 "register_operand")))
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;; Only use branch-on-bit sequences when the mask is not an ANDI immediate.
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(define_predicate "branch_on_bit_operand"
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(and (match_code "const_int")
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(match_test "INTVAL (op) >= IMM_BITS - 1")))
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;; This is used for indexing into vectors, and hence only accepts const_int.
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(define_predicate "const_0_or_1_operand"
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(and (match_code "const_int")
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(ior (match_test "op == CONST0_RTX (GET_MODE (op))")
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(match_test "op == CONST1_RTX (GET_MODE (op))"))))
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(define_special_predicate "pc_or_label_operand"
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(match_code "pc,label_ref"))
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;; A legitimate CONST_INT operand that takes more than one instruction
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;; to load.
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(define_predicate "splittable_const_int_operand"
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(match_code "const_int")
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{
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/* Don't handle multi-word moves this way; we don't want to introduce
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the individual word-mode moves until after reload. */
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if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
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return false;
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/* Otherwise check whether the constant can be loaded in a single
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instruction. */
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return !LUI_INT (op) && !SMALL_INT (op);
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})
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(define_predicate "move_operand"
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(match_operand 0 "general_operand")
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{
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enum riscv_symbol_type symbol_type;
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/* The thinking here is as follows:
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(1) The move expanders should split complex load sequences into
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individual instructions. Those individual instructions can
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then be optimized by all rtl passes.
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(2) The target of pre-reload load sequences should not be used
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to store temporary results. If the target register is only
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assigned one value, reload can rematerialize that value
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on demand, rather than spill it to the stack.
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(3) If we allowed pre-reload passes like combine and cse to recreate
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complex load sequences, we would want to be able to split the
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sequences before reload as well, so that the pre-reload scheduler
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can see the individual instructions. This falls foul of (2);
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the splitter would be forced to reuse the target register for
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intermediate results.
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(4) We want to define complex load splitters for combine. These
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splitters can request a temporary scratch register, which avoids
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the problem in (2). They allow things like:
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(set (reg T1) (high SYM))
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(set (reg T2) (low (reg T1) SYM))
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(set (reg X) (plus (reg T2) (const_int OFFSET)))
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to be combined into:
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(set (reg T3) (high SYM+OFFSET))
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(set (reg X) (lo_sum (reg T3) SYM+OFFSET))
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if T2 is only used this once. */
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switch (GET_CODE (op))
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{
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case CONST_INT:
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return !splittable_const_int_operand (op, mode);
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case CONST:
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case SYMBOL_REF:
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case LABEL_REF:
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return (riscv_symbolic_constant_p (op, &symbol_type)
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&& !riscv_hi_relocs[symbol_type]);
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case HIGH:
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op = XEXP (op, 0);
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return riscv_symbolic_constant_p (op, &symbol_type);
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default:
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return true;
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}
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})
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(define_predicate "consttable_operand"
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(match_test "CONSTANT_P (op)"))
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(define_predicate "symbolic_operand"
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(match_code "const,symbol_ref,label_ref")
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{
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enum riscv_symbol_type type;
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return riscv_symbolic_constant_p (op, &type);
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})
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(define_predicate "absolute_symbolic_operand"
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(match_code "const,symbol_ref,label_ref")
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{
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enum riscv_symbol_type type;
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return (riscv_symbolic_constant_p (op, &type)
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&& type == SYMBOL_ABSOLUTE);
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})
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(define_predicate "plt_symbolic_operand"
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(match_code "const,symbol_ref,label_ref")
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{
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enum riscv_symbol_type type;
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return (riscv_symbolic_constant_p (op, &type)
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&& type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT);
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})
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(define_predicate "call_insn_operand"
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(ior (match_operand 0 "absolute_symbolic_operand")
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(match_operand 0 "plt_symbolic_operand")
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(match_operand 0 "register_operand")))
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(define_predicate "symbol_ref_operand"
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(match_code "symbol_ref"))
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(define_predicate "modular_operator"
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(match_code "plus,minus,mult,ashift"))
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(define_predicate "equality_operator"
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(match_code "eq,ne"))
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(define_predicate "order_operator"
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(match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
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(define_predicate "fp_order_operator"
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(match_code "eq,ne,lt,le,gt,ge"))
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