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serginhofr |
; Options for the MIPS port of the compiler
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;
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; Copyright (C) 2005, 2007, 2008, 2010, 2011 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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; License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; .
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m32
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Target RejectNegative Mask(32BIT)
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Generate RV32 code
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m64
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Target RejectNegative InverseMask(32BIT, 64BIT)
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Generate RV64 code
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mbranch-cost=
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Target RejectNegative Joined UInteger Var(riscv_branch_cost)
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-mbranch-cost=COST Set the cost of branches to roughly COST instructions
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mhard-float
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Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
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Allow the use of hardware floating-point ABI and instructions
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mmemcpy
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Target Report Mask(MEMCPY)
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Don't optimize block moves
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mplt
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Target Report Var(TARGET_PLT) Init(1)
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When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
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msoft-float
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Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
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Prevent the use of all hardware floating-point instructions
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mno-fdiv
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Target Report RejectNegative Mask(NO_FDIV)
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Don't use hardware floating-point divide and square root instructions
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mfdiv
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Target Report RejectNegative InverseMask(NO_FDIV, FDIV)
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Use hardware floating-point divide and square root instructions
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march=
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Target RejectNegative Joined Var(riscv_arch_string)
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-march= Generate code for given RISC-V ISA (e.g. RV64IM)
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mtune=
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Target RejectNegative Joined Var(riscv_tune_string)
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-mtune=PROCESSOR Optimize the output for PROCESSOR
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msmall-data-limit=
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Target Joined Separate UInteger Var(g_switch_value) Init(8)
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-msmall-data-limit= Put global and static data smaller than bytes into a special section (on some targets)
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matomic
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Target Report Mask(ATOMIC)
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Use hardware atomic memory instructions.
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mmuldiv
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Target Report Mask(MULDIV)
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Use hardware instructions for integer multiplication and division.
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mrvc
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Target Report Mask(RVC)
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Use compressed instruction encoding
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msave-restore
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Target Report Mask(SAVE_RESTORE)
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Use smaller but slower prologue and epilogue code
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mlra
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Target Report Var(riscv_lra_flag) Init(0) Save
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Use LRA instead of reload
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mcmodel=
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Target RejectNegative Joined Var(riscv_cmodel_string)
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Use given RISC-V code model (medlow or medany)
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