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1 2 hmanske
------------------------------------------------------------------
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-- PROJECT:      HiCoVec (highly configurable vector processor)
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--
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-- ENTITY:      flag
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--
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-- PURPOSE:     one bit flag for status register
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--              carry or zero
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--
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-- AUTHOR:      harald manske, haraldmanske@gmx.de
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--
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-- VERSION:     1.0
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-----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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entity flag is
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    port(   clk:        in std_logic;
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            load:       in std_logic;
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            data_in:    in std_logic;
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            data_out:   out std_logic
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         );
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end flag;
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architecture rtl of flag is
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    signal q:  std_logic;
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begin
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    process
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    begin
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        wait until clk='1' and clk'event;
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        if load = '1' then
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            q <= data_in;
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        else
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            q <= q;
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        end if;
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        end process;
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    data_out <= q;
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end rtl;
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