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----------------------------------------------------------------------------------
-- Company:        Fachhochschule Augsburg - Fakult�t f�r Informatik
-- Engineer:       Sch�ferling Michael
-- 
-- Create Date:    23:34:55 02/27/2007 
-- Design Name:    
-- Module Name:    rs232 - Behavioral 
-- Project Name:   
-- Target Devices: Xilinx
-- Tool versions:  
-- Description:    This module provides RS232 communication
--
-- Dependencies:   
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity rs232 is
  generic(DATABITS:  integer:= 8;
                         STARTBITS: integer:= 1;
                         STOPBITS:  integer:= 1
  );
 
  port( -- HW signalling 
                        CLK_50MHZ        : in  std_logic;
                        RS232_RXD: in  std_logic;
                        RS232_TXD: out std_logic := '1';
 
                  -- internal DataCom
                        DATA_TX          : in  std_logic_vector(DATABITS-1 downto 0);
                        TX_SEND_DATA : in  std_logic;
                        TX_BUSY          : out std_logic := '0';
 
                        DATA_RX          : out std_logic_vector(DATABITS-1 downto 0) := (others => '0');
                        RX_DATA_RCVD : out std_logic := '0';
                        RX_BUSY          : out std_logic := '0'
  );
end rs232;
 
 
 
architecture Behavioral of rs232 is
 
type SER_STATES is (IDLE, SYN, B0, B1, B2, B3, B4, B5, B6, B7, VALID);
 
signal SER_STATE: SER_STATES := IDLE;
 
 
signal CLK_38400: std_logic := '0';
signal SIG_RST_TSER2: std_logic := '0';
signal SIG_TSER2: std_logic := '0';
 
signal SIG_RST_TSER: std_logic := '0';
signal SIG_TSER: std_logic := '0';
 
 
begin
 
 
 
-- Generate Signal for Serial Clock at 38400
P_GEN_CLK38400: process (CLK_50MHZ)
-- 1302 == 10100010110
constant CLK38400_MAX: std_logic_vector(10 downto 0) := "10100010110";
variable CLK38400_CUR: std_logic_vector(10 downto 0) := "00000000000";
begin
  if CLK_50MHZ'event AND CLK_50MHZ='1' then
         if CLK38400_CUR = CLK38400_MAX then
           CLK38400_CUR := (others => '0');
                CLK_38400 <= '1';
         else
           CLK38400_CUR := CLK38400_CUR + "00000000001";
                CLK_38400 <= '0';
         end if;
  end if;
end process P_GEN_CLK38400;
 
 
 
-- Generate Reset-driven Signal after Tser/2
P_GEN_SIG_TSER2: process (CLK_50MHZ)
-- 651 == 1010001011
constant TSER2_MAX: std_logic_vector(9 downto 0) := "1010001011";
variable TSER2_CUR: std_logic_vector(9 downto 0) := "0000000000";
begin
  if CLK_50MHZ'event AND CLK_50MHZ='1' then
         if SIG_RST_TSER2 = '1' then
                SIG_TSER2 <= '0';
           TSER2_CUR := (others => '0');
         elsif TSER2_CUR = TSER2_MAX then
           SIG_TSER2 <= '1';
                TSER2_CUR := (others => '0');
         else
                SIG_TSER2 <= '0';
           TSER2_CUR := TSER2_CUR + "0000000001";
         end if;
  end if;
end process P_GEN_SIG_TSER2;
 
 
 
-- Generate Reset-driven Signal after Tser
P_GEN_SIG_TSER: process (CLK_50MHZ)
constant TSER_MAX: std_logic_vector(10 downto 0) := "10100010110";
variable TSER_CUR: std_logic_vector(10 downto 0) := "00000000000";
begin
  if CLK_50MHZ'event AND CLK_50MHZ='1' then
         if SIG_RST_TSER = '1' then
                SIG_TSER <= '0';
           TSER_CUR := (others => '0');
         elsif TSER_CUR = TSER_MAX then
                SIG_TSER <= '1';
           TSER_CUR := (others => '0');
         else
                SIG_TSER <= '0';
           TSER_CUR := TSER_CUR + "00000000001";
         end if;
  end if;
end process P_GEN_SIG_TSER;
 
 
 
-- RX / TX Process
P_RX_TX: process (CLK_50MHZ)
constant TOKENSIZE: integer:= STARTBITS + DATABITS + STOPBITS;
 
-- variables for RX
variable BYTE_RX: std_logic_vector(7 downto 0);
  -- for testing
variable signcount: std_logic_vector(3 downto 0) := "0000";
 
-- variables for TX
variable SEND_TOKEN: std_logic := '0';
variable TOKEN_OUT: std_logic_vector(TOKENSIZE-1 downto 0);
variable COUNT: std_logic_vector(3 downto 0) := "0000";
 
begin
  if CLK_50MHZ'event AND CLK_50MHZ='1' then
 -- RX
         RX_BUSY <= '1';
    case SER_STATE is
           when IDLE =>   if RS232_RXD = '0' then
                                                                SIG_RST_TSER2 <= '1';
                                                                SER_STATE <= SYN;
                                                                RX_DATA_RCVD <= '0';
                                                        else
                                                                RX_BUSY <= '0';
                                                                SIG_RST_TSER2 <= '0';
                                                                SER_STATE <= IDLE;
                                                                RX_DATA_RCVD <= '0';
                                                        end if;
                when SYN  =>   if SIG_TSER2 = '1' then
                                                                SIG_RST_TSER2 <= '0';
                                                                SIG_RST_TSER <= '1';
                                                                SER_STATE <= B0;
                                                        else
                                                                SIG_RST_TSER2 <= '0';
                                                                SIG_RST_TSER <= '0';
                                                                SER_STATE <= SYN;
                                                        end if;
                when B0   =>   if SIG_TSER = '1' then
                                                                SIG_RST_TSER <= '0';
                                                                SER_STATE <= B1;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else
                                                                SIG_RST_TSER <= '0';
                                                                SER_STATE <= B0;
                                                        end if;
                when B1   =>   if SIG_TSER = '1' then
                                                                SER_STATE <= B2;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else SER_STATE <= B1;
                                                        end if;
                when B2   =>   if SIG_TSER = '1' then
                                                                SER_STATE <= B3;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else SER_STATE <= B2;
                                                        end if;
                when B3   =>   if SIG_TSER = '1' then
                                                                SER_STATE <= B4;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else SER_STATE <= B3;
                                                        end if;
                when B4   =>   if SIG_TSER = '1' then
                                                                SER_STATE <= B5;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else SER_STATE <= B4;
                                                        end if;
                when B5   =>   if SIG_TSER = '1' then
                                                                SER_STATE <= B6;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else SER_STATE <= B5;
                                                        end if;
                when B6   =>   if SIG_TSER = '1' then
                                                                SER_STATE <= B7;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else SER_STATE <= B6;
                                                        end if;
                when B7   =>   if SIG_TSER = '1' then
                                                                SER_STATE <= VALID;
                                                                BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
                                                        else SER_STATE <= B7;
                                                        end if;
                when VALID =>  if SIG_TSER = '1' then
                                                                if RS232_RXD = '1' then
                                                                        DATA_RX <= BYTE_RX;
                                                                        RX_DATA_RCVD <= '1';
                                                                else
                                                                   DATA_RX <= (others => '0');
                                                                        RX_DATA_RCVD <= '0';
                                                                end if;
                                                                SER_STATE <= IDLE;
                                                        else
                                                                SER_STATE <= VALID;
                                                        end if;
                end case;
 
 
 -- TX
                TX_BUSY <= '0';
      if TX_SEND_DATA = '1' AND SEND_TOKEN = '0' then
                  TOKEN_OUT := '1' & DATA_TX & '0';
                  SEND_TOKEN := '1';
                end if;
 
                if SEND_TOKEN = '1' then
                        TX_BUSY <= '1';
                        if CLK_38400 = '1' then
                      if COUNT < TOKENSIZE then
                         --TX_BUSY <= '1';
                         COUNT := COUNT + "0001";
                                        -- send from right to left (LSB first)
               RS232_TXD <= TOKEN_OUT(0);
                    TOKEN_OUT(TOKENSIZE-1 downto 0) := TOKEN_OUT(0) & TOKEN_OUT(TOKENSIZE-1 downto 1);
                 else
                         COUNT := "0000";
                                        SEND_TOKEN := '0';
                                        --TX_BUSY <= '0';
                 end if;
                        end if;
                --else
                        --TX_BUSY <= '0';
           end if;
   end if;
end process P_RX_TX;
 
end Behavioral;

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Subversion Repositories hicovec

[/] [hicovec/] [branches/] [avendor/] [cpu/] [units/] [rs232.vhd] - Blame information for rev 12

Line No.	Rev	Author	Line
1	2	hmanske	`----------------------------------------------------------------------------------`
2			`-- Company: Fachhochschule Augsburg - Fakult�t f�r Informatik`
3			`-- Engineer: Sch�ferling Michael`
4			`--`
5			`-- Create Date: 23:34:55 02/27/2007`
6			`-- Design Name:`
7			`-- Module Name: rs232 - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices: Xilinx`
10			`-- Tool versions:`
11			`-- Description: This module provides RS232 communication`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`---- Uncomment the following library declaration if instantiating`
26			`---- any Xilinx primitives in this code.`
27			`--library UNISIM;`
28			`--use UNISIM.VComponents.all;`
29
30			`entity rs232 is`
31			`generic(DATABITS: integer:= 8;`
32			`STARTBITS: integer:= 1;`
33			`STOPBITS: integer:= 1`
34			`);`
35
36			`port( -- HW signalling`
37			`CLK_50MHZ : in std_logic;`
38			`RS232_RXD: in std_logic;`
39			`RS232_TXD: out std_logic := '1';`
40
41			`-- internal DataCom`
42			`DATA_TX : in std_logic_vector(DATABITS-1 downto 0);`
43			`TX_SEND_DATA : in std_logic;`
44			`TX_BUSY : out std_logic := '0';`
45
46			`DATA_RX : out std_logic_vector(DATABITS-1 downto 0) := (others => '0');`
47			`RX_DATA_RCVD : out std_logic := '0';`
48			`RX_BUSY : out std_logic := '0'`
49			`);`
50			`end rs232;`
51
52
53
54			`architecture Behavioral of rs232 is`
55
56			`type SER_STATES is (IDLE, SYN, B0, B1, B2, B3, B4, B5, B6, B7, VALID);`
57
58			`signal SER_STATE: SER_STATES := IDLE;`
59
60
61			`signal CLK_38400: std_logic := '0';`
62			`signal SIG_RST_TSER2: std_logic := '0';`
63			`signal SIG_TSER2: std_logic := '0';`
64
65			`signal SIG_RST_TSER: std_logic := '0';`
66			`signal SIG_TSER: std_logic := '0';`
67
68
69			`begin`
70
71
72
73			`-- Generate Signal for Serial Clock at 38400`
74			`P_GEN_CLK38400: process (CLK_50MHZ)`
75			`-- 1302 == 10100010110`
76			`constant CLK38400_MAX: std_logic_vector(10 downto 0) := "10100010110";`
77			`variable CLK38400_CUR: std_logic_vector(10 downto 0) := "00000000000";`
78			`begin`
79			`if CLK_50MHZ'event AND CLK_50MHZ='1' then`
80			`if CLK38400_CUR = CLK38400_MAX then`
81			`CLK38400_CUR := (others => '0');`
82			`CLK_38400 <= '1';`
83			`else`
84			`CLK38400_CUR := CLK38400_CUR + "00000000001";`
85			`CLK_38400 <= '0';`
86			`end if;`
87			`end if;`
88			`end process P_GEN_CLK38400;`
89
90
91
92			`-- Generate Reset-driven Signal after Tser/2`
93			`P_GEN_SIG_TSER2: process (CLK_50MHZ)`
94			`-- 651 == 1010001011`
95			`constant TSER2_MAX: std_logic_vector(9 downto 0) := "1010001011";`
96			`variable TSER2_CUR: std_logic_vector(9 downto 0) := "0000000000";`
97			`begin`
98			`if CLK_50MHZ'event AND CLK_50MHZ='1' then`
99			`if SIG_RST_TSER2 = '1' then`
100			`SIG_TSER2 <= '0';`
101			`TSER2_CUR := (others => '0');`
102			`elsif TSER2_CUR = TSER2_MAX then`
103			`SIG_TSER2 <= '1';`
104			`TSER2_CUR := (others => '0');`
105			`else`
106			`SIG_TSER2 <= '0';`
107			`TSER2_CUR := TSER2_CUR + "0000000001";`
108			`end if;`
109			`end if;`
110			`end process P_GEN_SIG_TSER2;`
111
112
113
114			`-- Generate Reset-driven Signal after Tser`
115			`P_GEN_SIG_TSER: process (CLK_50MHZ)`
116			`constant TSER_MAX: std_logic_vector(10 downto 0) := "10100010110";`
117			`variable TSER_CUR: std_logic_vector(10 downto 0) := "00000000000";`
118			`begin`
119			`if CLK_50MHZ'event AND CLK_50MHZ='1' then`
120			`if SIG_RST_TSER = '1' then`
121			`SIG_TSER <= '0';`
122			`TSER_CUR := (others => '0');`
123			`elsif TSER_CUR = TSER_MAX then`
124			`SIG_TSER <= '1';`
125			`TSER_CUR := (others => '0');`
126			`else`
127			`SIG_TSER <= '0';`
128			`TSER_CUR := TSER_CUR + "00000000001";`
129			`end if;`
130			`end if;`
131			`end process P_GEN_SIG_TSER;`
132
133
134
135			`-- RX / TX Process`
136			`P_RX_TX: process (CLK_50MHZ)`
137			`constant TOKENSIZE: integer:= STARTBITS + DATABITS + STOPBITS;`
138
139			`-- variables for RX`
140			`variable BYTE_RX: std_logic_vector(7 downto 0);`
141			`-- for testing`
142			`variable signcount: std_logic_vector(3 downto 0) := "0000";`
143
144			`-- variables for TX`
145			`variable SEND_TOKEN: std_logic := '0';`
146			`variable TOKEN_OUT: std_logic_vector(TOKENSIZE-1 downto 0);`
147			`variable COUNT: std_logic_vector(3 downto 0) := "0000";`
148
149			`begin`
150			`if CLK_50MHZ'event AND CLK_50MHZ='1' then`
151			`-- RX`
152			`RX_BUSY <= '1';`
153			`case SER_STATE is`
154			`when IDLE => if RS232_RXD = '0' then`
155			`SIG_RST_TSER2 <= '1';`
156			`SER_STATE <= SYN;`
157			`RX_DATA_RCVD <= '0';`
158			`else`
159			`RX_BUSY <= '0';`
160			`SIG_RST_TSER2 <= '0';`
161			`SER_STATE <= IDLE;`
162			`RX_DATA_RCVD <= '0';`
163			`end if;`
164			`when SYN => if SIG_TSER2 = '1' then`
165			`SIG_RST_TSER2 <= '0';`
166			`SIG_RST_TSER <= '1';`
167			`SER_STATE <= B0;`
168			`else`
169			`SIG_RST_TSER2 <= '0';`
170			`SIG_RST_TSER <= '0';`
171			`SER_STATE <= SYN;`
172			`end if;`
173			`when B0 => if SIG_TSER = '1' then`
174			`SIG_RST_TSER <= '0';`
175			`SER_STATE <= B1;`
176			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
177			`else`
178			`SIG_RST_TSER <= '0';`
179			`SER_STATE <= B0;`
180			`end if;`
181			`when B1 => if SIG_TSER = '1' then`
182			`SER_STATE <= B2;`
183			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
184			`else SER_STATE <= B1;`
185			`end if;`
186			`when B2 => if SIG_TSER = '1' then`
187			`SER_STATE <= B3;`
188			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
189			`else SER_STATE <= B2;`
190			`end if;`
191			`when B3 => if SIG_TSER = '1' then`
192			`SER_STATE <= B4;`
193			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
194			`else SER_STATE <= B3;`
195			`end if;`
196			`when B4 => if SIG_TSER = '1' then`
197			`SER_STATE <= B5;`
198			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
199			`else SER_STATE <= B4;`
200			`end if;`
201			`when B5 => if SIG_TSER = '1' then`
202			`SER_STATE <= B6;`
203			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
204			`else SER_STATE <= B5;`
205			`end if;`
206			`when B6 => if SIG_TSER = '1' then`
207			`SER_STATE <= B7;`
208			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
209			`else SER_STATE <= B6;`
210			`end if;`
211			`when B7 => if SIG_TSER = '1' then`
212			`SER_STATE <= VALID;`
213			`BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);`
214			`else SER_STATE <= B7;`
215			`end if;`
216			`when VALID => if SIG_TSER = '1' then`
217			`if RS232_RXD = '1' then`
218			`DATA_RX <= BYTE_RX;`
219			`RX_DATA_RCVD <= '1';`
220			`else`
221			`DATA_RX <= (others => '0');`
222			`RX_DATA_RCVD <= '0';`
223			`end if;`
224			`SER_STATE <= IDLE;`
225			`else`
226			`SER_STATE <= VALID;`
227			`end if;`
228			`end case;`
229
230
231			`-- TX`
232			`TX_BUSY <= '0';`
233			`if TX_SEND_DATA = '1' AND SEND_TOKEN = '0' then`
234			`TOKEN_OUT := '1' & DATA_TX & '0';`
235			`SEND_TOKEN := '1';`
236			`end if;`
237
238			`if SEND_TOKEN = '1' then`
239			`TX_BUSY <= '1';`
240			`if CLK_38400 = '1' then`
241			`if COUNT < TOKENSIZE then`
242			`--TX_BUSY <= '1';`
243			`COUNT := COUNT + "0001";`
244			`-- send from right to left (LSB first)`
245			`RS232_TXD <= TOKEN_OUT(0);`
246			`TOKEN_OUT(TOKENSIZE-1 downto 0) := TOKEN_OUT(0) & TOKEN_OUT(TOKENSIZE-1 downto 1);`
247			`else`
248			`COUNT := "0000";`
249			`SEND_TOKEN := '0';`
250			`--TX_BUSY <= '0';`
251			`end if;`
252			`end if;`
253			`--else`
254			`--TX_BUSY <= '0';`
255			`end if;`
256			`end if;`
257			`end process P_RX_TX;`
258
259			`end Behavioral;`