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[/] [hicovec/] [trunk/] [cpu/] [groups/] [vector_executionunit.vhd] - Blame information for rev 12

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------------------------------------------------------------------
-- PROJECT:      HiCoVec (highly configurable vector processor)
--
-- ENTITY:      vector_executionunit
--
-- PURPOSE:     execution unit of the vector unit
--
-- AUTHOR:      harald manske, haraldmanske@gmx.de
--
-- VERSION:     1.0
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
use work.cfg.all;
use work.datatypes.all;
 
entity vector_executionunit is
    port (
        -- clock
        clk:        in std_logic;
 
        -- data inputs
        memory_in:  in vectordata_type;
        scalar_in:  in std_logic_vector(31 downto 0);
 
        -- data outputs
        memory_out: out vectordata_type;
        scalar_out: out std_logic_vector(31 downto 0);
        out_valid:  out std_logic;
        shuffle_valid:  out std_logic;
 
        -- control signals
        rrrr:       in std_logic_vector(3 downto 0);
        vvvv:       in std_logic_vector(3 downto 0);
        wwww:       in std_logic_vector(3 downto 0);
        k_in:       in std_logic_vector(31 downto 0);
        vn:         in std_logic_vector(7 downto 0);    -- immediate value n for vector unit
        valuop:     in std_logic_vector(3 downto 0);
        vwidth:     in std_logic_vector(1 downto 0);
        load_r:     in std_logic;
        cc9:        in std_logic_vector(1 downto 0);
        c10:        in std_logic;
        c11:        in std_logic;
        c12:        in std_logic;
        cc13:       in std_logic_vector(1 downto 0);
        valu_go:    in std_logic;
        shuffle_go: in std_logic
    );
end vector_executionunit;
 
architecture rtl of vector_executionunit is
    component selectunit
        port (
            data_in :   in  vectordata_type;
            k_in:       in  std_logic_vector(31 downto 0);
            data_out:   out std_logic_vector(31 downto 0)
        );
    end component;
 
    component shuffle
        port (
            clk:                in  std_logic;
            shuffle_go:         in  std_logic;
            shuffle_valid:      out std_logic;
            data_in_v:          in  vectordata_type;
            data_in_w:          in  vectordata_type;
            vn:                 in  std_logic_vector(7 downto 0);
            ssss:               in  std_logic_vector(3 downto 0);
            vwidth:             in  std_logic_vector(1 downto 0);
            shuffle_out_sel:    in  std_logic_vector(1 downto 0);
            data_out:           out vectordata_type
        );
    end component;
 
    component valu_controlunit
        port(
            clk:                in std_logic;
            valu_go:            in std_logic;
            valuop:             in std_logic_vector(3 downto 0);
            vwidth:             in std_logic_vector(1 downto 0);
            source_sel:         out std_logic_vector(1 downto 0);
            carry_sel:          out std_logic_vector(1 downto 0);
            mult_source_sel:    out std_logic_vector(1 downto 0);
            mult_dest_sel:      out std_logic_vector(1 downto 0);
            reg_input_sel:      out std_logic;
            load_lsr:           out std_logic;
            load_other:         out std_logic;
            out_valid:          out std_logic
        );
    end component;
 
    component vector_slice
        generic (
            slicenr : natural := 0
        );
        port (
            clk:                in std_logic;
            memory_in:          in std_logic_vector(31 downto 0);
            scalar_in:          in std_logic_vector(31 downto 0);
            shuffle_in:         in std_logic_vector(31 downto 0);
            carry_in:           in std_logic;
            rshift_in:          in std_logic;
            v_out:              out std_logic_vector(31 downto 0);
            w_out:              out std_logic_vector(31 downto 0);
            carry_out:          out std_logic;
            rrrr:               in std_logic_vector(7 downto 0);
            vvvv:               in std_logic_vector(7 downto 0);
            wwww:               in std_logic_vector(3 downto 0);
            k_in:               in std_logic_vector(31 downto 0);
            load_r:             in std_logic;
            cc9:                in std_logic_vector(1 downto 0);
            c12:                in std_logic;
            valuop:             in std_logic_vector(3 downto 0);
            source_sel:         in std_logic_vector(1 downto 0);
            carry_sel:          in std_logic_vector(1 downto 0);
            mult_source_sel:    in std_logic_vector(1 downto 0);
            mult_dest_sel:      in std_logic_vector(1 downto 0);
            reg_input_sel:      in std_logic;
            load_lsr:           in std_logic;
            load_other:         in std_logic
        );
    end component;
 
    component multiplexer2
        generic (
            w : positive
        );
        port(
            selector:   in std_logic;
            data_in_0:  in std_logic_vector(w-1 downto 0);
            data_in_1:  in std_logic_vector(w-1 downto 0);
            data_out:   out std_logic_vector(w-1 downto 0)
        );
    end component;
 
    for shuffle_impl: shuffle use entity work.shuffle(rtl);
    for selectunit_impl: selectunit use entity work.selectunit(rtl);
    for valu_controlunit_impl: valu_controlunit use entity work.valu_controlunit(rtl);
 
    for rrrr_mux: multiplexer2 use entity work.multiplexer2(rtl);
    for vvvv_mux: multiplexer2 use entity work.multiplexer2(rtl);
 
    signal carry :  std_logic_vector(k-1 downto 0);
    signal v_vector : vectordata_type;
    signal w_vector : vectordata_type;
    signal shuffle_out : vectordata_type;
    signal select_v : std_logic_vector(7 downto 0);
    signal select_r : std_logic_vector(7 downto 0);
 
    signal sel_r : std_logic_vector(7 downto 0);
    signal sel_v : std_logic_vector(7 downto 0);
    signal sel_w : std_logic_vector(3 downto 0);
 
    signal rrrr_ext  : std_logic_vector(7 downto 0);
    signal vvvv_ext  : std_logic_vector(7 downto 0);
 
    signal source_sel: std_logic_vector(1 downto 0);
    signal carry_sel:  std_logic_vector(1 downto 0);
    signal mult_source_sel: std_logic_vector(1 downto 0);
    signal mult_dest_sel: std_logic_vector(1 downto 0);
    signal reg_input_sel: std_logic;
    signal load_lsr: std_logic;
    signal load_other: std_logic;
 
begin
    rrrr_ext <= "0000" & rrrr;
    vvvv_ext <= "0000" & vvvv;
 
    rrrr_mux : multiplexer2
        generic map (w => 8)
        port map (
            selector => c10,
            data_in_0 => rrrr_ext,
            data_in_1 => vn,
            data_out => select_r
        );
 
 
    vvvv_mux : multiplexer2
        generic map (w => 8)
        port map (
            selector => c11,
            data_in_0 => vvvv_ext,
            data_in_1 => vn,
            data_out => select_v
        );
 
    -- check index < n
    sel_r <= select_r when (select_r < n) else (others => '0');
    sel_v <= select_v when (select_v < n) else (others => '0');
    sel_w <= wwww when (wwww < n) else (others => '0');
 
    selectunit_impl: selectunit
        port map (
            data_in => v_vector,
            k_in => k_in,
            data_out => scalar_out
        );
 
    shuffle_impl: shuffle
        port map (
            clk => clk,
            shuffle_go => shuffle_go,
            shuffle_valid => shuffle_valid,
            data_in_v => v_vector,
            data_in_w => w_vector,
            vn => vn,
            ssss => valuop,
            vwidth => vwidth,
            shuffle_out_sel => cc13,
            data_out => shuffle_out
        );
 
    valu_controlunit_impl: valu_controlunit
        port map (
            clk => clk,
            valu_go         => valu_go,
            valuop          => valuop,
            vwidth          => vwidth,
            source_sel      => source_sel,
            carry_sel       => carry_sel,
            mult_source_sel => mult_source_sel,
            mult_dest_sel   => mult_dest_sel,
            reg_input_sel   => reg_input_sel,
            load_lsr        => load_lsr,
            load_other      => load_other,
            out_valid       => out_valid
        );
 
    vector_slice_impl: for i in k-1 downto 0 generate
        vector_slice_even: if i mod 2 = 0 generate
            slice_even: vector_slice
            generic map (
                slicenr => i
            )
            port map (
                clk => clk,
                memory_in       => memory_in(i),
                scalar_in       => scalar_in,
                shuffle_in      => shuffle_out(i),
                carry_in        => '0',
                rshift_in       => carry(i+1),
                v_out           => v_vector(i),
                w_out           => w_vector(i),
                carry_out       => carry(i),
                rrrr            => sel_r,
                vvvv            => sel_v,
                wwww            => sel_w,
                k_in            => k_in,
                load_r          => load_r,
                cc9             => cc9,
                c12             => c12,
                valuop          => valuop,
                source_sel      => source_sel,
                carry_sel       => carry_sel,
                mult_source_sel => mult_source_sel,
                mult_dest_sel   => mult_dest_sel,
                reg_input_sel   => reg_input_sel,
                load_lsr        => load_lsr,
                load_other      => load_other
            );
        end generate;
 
        vector_slice_uneven: if i mod 2 = 1 generate
            slice_uneven: vector_slice
            generic map (
                slicenr => i
            )
            port map (
                clk => clk,
                memory_in       => memory_in(i),
                scalar_in       => scalar_in,
                shuffle_in      => shuffle_out(i),
                carry_in        => carry(i-1),
                rshift_in       => '0',
                v_out           => v_vector(i),
                w_out           => w_vector(i),
                carry_out       => carry(i),
                rrrr            => sel_r,
                vvvv            => sel_v,
                wwww            => sel_w,
                k_in            => k_in,
                load_r          => load_r,
                cc9             => cc9,
                c12             => c12,
                valuop          => valuop,
                source_sel      => source_sel,
                carry_sel       => carry_sel,
                mult_source_sel => mult_source_sel,
                mult_dest_sel   => mult_dest_sel,
                reg_input_sel   => reg_input_sel,
                load_lsr        => load_lsr,
                load_other      => load_other
            );
        end generate;
    end generate ;
 
    memory_out <= v_vector;
 
end rtl;

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Subversion Repositories hicovec

[/] [hicovec/] [trunk/] [cpu/] [groups/] [vector_executionunit.vhd] - Blame information for rev 12

Line No.	Rev	Author	Line
1	2	hmanske	`------------------------------------------------------------------`
2	4	hmanske	`-- PROJECT: HiCoVec (highly configurable vector processor)`
3	2	hmanske	`--`
4			`-- ENTITY: vector_executionunit`
5			`--`
6			`-- PURPOSE: execution unit of the vector unit`
7			`--`
8			`-- AUTHOR: harald manske, haraldmanske@gmx.de`
9			`--`
10			`-- VERSION: 1.0`
11			`------------------------------------------------------------------`
12			`library ieee;`
13			`use ieee.std_logic_1164.all;`
14			`use ieee.std_logic_unsigned.all;`
15
16			`use work.cfg.all;`
17			`use work.datatypes.all;`
18
19			`entity vector_executionunit is`
20			`port (`
21			`-- clock`
22			`clk: in std_logic;`
23
24			`-- data inputs`
25			`memory_in: in vectordata_type;`
26			`scalar_in: in std_logic_vector(31 downto 0);`
27
28			`-- data outputs`
29			`memory_out: out vectordata_type;`
30			`scalar_out: out std_logic_vector(31 downto 0);`
31			`out_valid: out std_logic;`
32			`shuffle_valid: out std_logic;`
33
34			`-- control signals`
35			`rrrr: in std_logic_vector(3 downto 0);`
36			`vvvv: in std_logic_vector(3 downto 0);`
37			`wwww: in std_logic_vector(3 downto 0);`
38			`k_in: in std_logic_vector(31 downto 0);`
39			`vn: in std_logic_vector(7 downto 0); -- immediate value n for vector unit`
40			`valuop: in std_logic_vector(3 downto 0);`
41			`vwidth: in std_logic_vector(1 downto 0);`
42			`load_r: in std_logic;`
43			`cc9: in std_logic_vector(1 downto 0);`
44			`c10: in std_logic;`
45			`c11: in std_logic;`
46			`c12: in std_logic;`
47			`cc13: in std_logic_vector(1 downto 0);`
48			`valu_go: in std_logic;`
49			`shuffle_go: in std_logic`
50			`);`
51			`end vector_executionunit;`
52
53			`architecture rtl of vector_executionunit is`
54			`component selectunit`
55			`port (`
56			`data_in : in vectordata_type;`
57			`k_in: in std_logic_vector(31 downto 0);`
58			`data_out: out std_logic_vector(31 downto 0)`
59			`);`
60			`end component;`
61
62			`component shuffle`
63			`port (`
64			`clk: in std_logic;`
65			`shuffle_go: in std_logic;`
66			`shuffle_valid: out std_logic;`
67			`data_in_v: in vectordata_type;`
68			`data_in_w: in vectordata_type;`
69			`vn: in std_logic_vector(7 downto 0);`
70			`ssss: in std_logic_vector(3 downto 0);`
71			`vwidth: in std_logic_vector(1 downto 0);`
72			`shuffle_out_sel: in std_logic_vector(1 downto 0);`
73			`data_out: out vectordata_type`
74			`);`
75			`end component;`
76
77			`component valu_controlunit`
78			`port(`
79			`clk: in std_logic;`
80			`valu_go: in std_logic;`
81			`valuop: in std_logic_vector(3 downto 0);`
82			`vwidth: in std_logic_vector(1 downto 0);`
83			`source_sel: out std_logic_vector(1 downto 0);`
84			`carry_sel: out std_logic_vector(1 downto 0);`
85			`mult_source_sel: out std_logic_vector(1 downto 0);`
86			`mult_dest_sel: out std_logic_vector(1 downto 0);`
87			`reg_input_sel: out std_logic;`
88			`load_lsr: out std_logic;`
89			`load_other: out std_logic;`
90			`out_valid: out std_logic`
91			`);`
92			`end component;`
93
94			`component vector_slice`
95			`generic (`
96			`slicenr : natural := 0`
97			`);`
98			`port (`
99			`clk: in std_logic;`
100			`memory_in: in std_logic_vector(31 downto 0);`
101			`scalar_in: in std_logic_vector(31 downto 0);`
102			`shuffle_in: in std_logic_vector(31 downto 0);`
103			`carry_in: in std_logic;`
104			`rshift_in: in std_logic;`
105			`v_out: out std_logic_vector(31 downto 0);`
106			`w_out: out std_logic_vector(31 downto 0);`
107			`carry_out: out std_logic;`
108			`rrrr: in std_logic_vector(7 downto 0);`
109			`vvvv: in std_logic_vector(7 downto 0);`
110			`wwww: in std_logic_vector(3 downto 0);`
111			`k_in: in std_logic_vector(31 downto 0);`
112			`load_r: in std_logic;`
113			`cc9: in std_logic_vector(1 downto 0);`
114			`c12: in std_logic;`
115			`valuop: in std_logic_vector(3 downto 0);`
116			`source_sel: in std_logic_vector(1 downto 0);`
117			`carry_sel: in std_logic_vector(1 downto 0);`
118			`mult_source_sel: in std_logic_vector(1 downto 0);`
119			`mult_dest_sel: in std_logic_vector(1 downto 0);`
120			`reg_input_sel: in std_logic;`
121			`load_lsr: in std_logic;`
122			`load_other: in std_logic`
123			`);`
124			`end component;`
125
126			`component multiplexer2`
127			`generic (`
128			`w : positive`
129			`);`
130			`port(`
131			`selector: in std_logic;`
132			`data_in_0: in std_logic_vector(w-1 downto 0);`
133			`data_in_1: in std_logic_vector(w-1 downto 0);`
134			`data_out: out std_logic_vector(w-1 downto 0)`
135			`);`
136			`end component;`
137
138			`for shuffle_impl: shuffle use entity work.shuffle(rtl);`
139			`for selectunit_impl: selectunit use entity work.selectunit(rtl);`
140			`for valu_controlunit_impl: valu_controlunit use entity work.valu_controlunit(rtl);`
141
142			`for rrrr_mux: multiplexer2 use entity work.multiplexer2(rtl);`
143			`for vvvv_mux: multiplexer2 use entity work.multiplexer2(rtl);`
144
145			`signal carry : std_logic_vector(k-1 downto 0);`
146			`signal v_vector : vectordata_type;`
147			`signal w_vector : vectordata_type;`
148			`signal shuffle_out : vectordata_type;`
149			`signal select_v : std_logic_vector(7 downto 0);`
150			`signal select_r : std_logic_vector(7 downto 0);`
151
152			`signal sel_r : std_logic_vector(7 downto 0);`
153			`signal sel_v : std_logic_vector(7 downto 0);`
154			`signal sel_w : std_logic_vector(3 downto 0);`
155
156			`signal rrrr_ext : std_logic_vector(7 downto 0);`
157			`signal vvvv_ext : std_logic_vector(7 downto 0);`
158
159			`signal source_sel: std_logic_vector(1 downto 0);`
160			`signal carry_sel: std_logic_vector(1 downto 0);`
161			`signal mult_source_sel: std_logic_vector(1 downto 0);`
162			`signal mult_dest_sel: std_logic_vector(1 downto 0);`
163			`signal reg_input_sel: std_logic;`
164			`signal load_lsr: std_logic;`
165			`signal load_other: std_logic;`
166
167			`begin`
168			`rrrr_ext <= "0000" & rrrr;`
169			`vvvv_ext <= "0000" & vvvv;`
170
171			`rrrr_mux : multiplexer2`
172			`generic map (w => 8)`
173			`port map (`
174			`selector => c10,`
175			`data_in_0 => rrrr_ext,`
176			`data_in_1 => vn,`
177			`data_out => select_r`
178			`);`
179
180
181			`vvvv_mux : multiplexer2`
182			`generic map (w => 8)`
183			`port map (`
184			`selector => c11,`
185			`data_in_0 => vvvv_ext,`
186			`data_in_1 => vn,`
187			`data_out => select_v`
188			`);`
189
190			`-- check index < n`
191			`sel_r <= select_r when (select_r < n) else (others => '0');`
192			`sel_v <= select_v when (select_v < n) else (others => '0');`
193			`sel_w <= wwww when (wwww < n) else (others => '0');`
194
195			`selectunit_impl: selectunit`
196			`port map (`
197			`data_in => v_vector,`
198			`k_in => k_in,`
199			`data_out => scalar_out`
200			`);`
201
202			`shuffle_impl: shuffle`
203			`port map (`
204			`clk => clk,`
205			`shuffle_go => shuffle_go,`
206			`shuffle_valid => shuffle_valid,`
207			`data_in_v => v_vector,`
208			`data_in_w => w_vector,`
209			`vn => vn,`
210			`ssss => valuop,`
211			`vwidth => vwidth,`
212			`shuffle_out_sel => cc13,`
213			`data_out => shuffle_out`
214			`);`
215
216			`valu_controlunit_impl: valu_controlunit`
217			`port map (`
218			`clk => clk,`
219			`valu_go => valu_go,`
220			`valuop => valuop,`
221			`vwidth => vwidth,`
222			`source_sel => source_sel,`
223			`carry_sel => carry_sel,`
224			`mult_source_sel => mult_source_sel,`
225			`mult_dest_sel => mult_dest_sel,`
226			`reg_input_sel => reg_input_sel,`
227			`load_lsr => load_lsr,`
228			`load_other => load_other,`
229			`out_valid => out_valid`
230			`);`
231
232			`vector_slice_impl: for i in k-1 downto 0 generate`
233			`vector_slice_even: if i mod 2 = 0 generate`
234			`slice_even: vector_slice`
235			`generic map (`
236			`slicenr => i`
237			`)`
238			`port map (`
239			`clk => clk,`
240			`memory_in => memory_in(i),`
241			`scalar_in => scalar_in,`
242			`shuffle_in => shuffle_out(i),`
243			`carry_in => '0',`
244			`rshift_in => carry(i+1),`
245			`v_out => v_vector(i),`
246			`w_out => w_vector(i),`
247			`carry_out => carry(i),`
248			`rrrr => sel_r,`
249			`vvvv => sel_v,`
250			`wwww => sel_w,`
251			`k_in => k_in,`
252			`load_r => load_r,`
253			`cc9 => cc9,`
254			`c12 => c12,`
255			`valuop => valuop,`
256			`source_sel => source_sel,`
257			`carry_sel => carry_sel,`
258			`mult_source_sel => mult_source_sel,`
259			`mult_dest_sel => mult_dest_sel,`
260			`reg_input_sel => reg_input_sel,`
261			`load_lsr => load_lsr,`
262			`load_other => load_other`
263			`);`
264			`end generate;`
265
266			`vector_slice_uneven: if i mod 2 = 1 generate`
267			`slice_uneven: vector_slice`
268			`generic map (`
269			`slicenr => i`
270			`)`
271			`port map (`
272			`clk => clk,`
273			`memory_in => memory_in(i),`
274			`scalar_in => scalar_in,`
275			`shuffle_in => shuffle_out(i),`
276			`carry_in => carry(i-1),`
277			`rshift_in => '0',`
278			`v_out => v_vector(i),`
279			`w_out => w_vector(i),`
280			`carry_out => carry(i),`
281			`rrrr => sel_r,`
282			`vvvv => sel_v,`
283			`wwww => sel_w,`
284			`k_in => k_in,`
285			`load_r => load_r,`
286			`cc9 => cc9,`
287			`c12 => c12,`
288			`valuop => valuop,`
289			`source_sel => source_sel,`
290			`carry_sel => carry_sel,`
291			`mult_source_sel => mult_source_sel,`
292			`mult_dest_sel => mult_dest_sel,`
293			`reg_input_sel => reg_input_sel,`
294			`load_lsr => load_lsr,`
295			`load_other => load_other`
296			`);`
297			`end generate;`
298			`end generate ;`
299
300			`memory_out <= v_vector;`
301
302			`end rtl;`