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[/] [hicovec/] [trunk/] [cpu/] [testbenches/] [tb_vector_alu_32.vhd] - Blame information for rev 2

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------------------------------------------------------------------
-- PROJECT:     clvp (configurable lightweight vector processor)
--
-- ENTITY:      tb_vector_alu_32
--
-- PURPOSE:     testbench of vector_alu_32 entity 
--
-- AUTHOR:      harald manske, haraldmanske@gmx.de
--
-- VERSION:     
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity tb_vector_alu_32 is
end tb_vector_alu_32;
 
architecture testbench of tb_vector_alu_32 is
    component vector_alu_32
        port (
                clk:                in std_logic;
                v_in:               in std_logic_vector(31 downto 0);
                w_in:               in std_logic_vector(31 downto 0);
                carry_in:           in std_logic;
                rshift_in:          in std_logic;
                carry_out:          out std_logic;
                valu_out:           out std_logic_vector(31 downto 0);
                valuop:             in std_logic_vector(3 downto 0);
                source_sel:         in std_logic_vector(1 downto 0);
                carry_sel:          in std_logic_vector(1 downto 0);
                mult_source_sel:    in std_logic_vector(1 downto 0);
                mult_dest_sel:      in std_logic_vector(1 downto 0);
                reg_input_sel:      in std_logic;
                load_lsr:           in std_logic;
                load_other:         in std_logic
        );
    end component;
 
    component valu_controlunit
        port(
            clk:                in std_logic;
            valu_go:            in std_logic;
            valuop:             in std_logic_vector(3 downto 0);
            vwidth:             in std_logic_vector(1 downto 0);
            source_sel:         out std_logic_vector(1 downto 0);
            carry_sel:          out std_logic_vector(1 downto 0);
            mult_source_sel:    out std_logic_vector(1 downto 0);
            mult_dest_sel:      out std_logic_vector(1 downto 0);
            reg_input_sel:      out std_logic;
            load_lsr:           out std_logic;
            load_other:         out std_logic;
            out_valid:          out std_logic
        );
    end component;
 
    for valu_controlunit_impl: valu_controlunit use entity work.valu_controlunit(rtl);
    for alu_impl: vector_alu_32 use entity work.vector_alu_32(rtl);
 
    signal clk:             std_logic;
    signal valu_go:         std_logic;
    signal vwidth:          std_logic_vector(1 downto 0);
    signal out_valid:       std_logic;
    signal v_in:            std_logic_vector(31 downto 0);
    signal w_in:            std_logic_vector(31 downto 0);
    signal carry_in:        std_logic;
    signal rshift_in:       std_logic;
    signal carry_out:       std_logic;
    signal valu_out:        std_logic_vector(31 downto 0);
    signal valuop:          std_logic_vector(3 downto 0);
    signal source_sel:      std_logic_vector(1 downto 0);
    signal carry_sel:       std_logic_vector(1 downto 0);
    signal load_lsr:        std_logic;
    signal load_other:      std_logic;
    signal mult_source_sel: std_logic_vector(1 downto 0);
    signal mult_dest_sel:   std_logic_vector(1 downto 0);
    signal reg_input_sel:   std_logic := '0';
 
    constant period     : time := 2ns;
 
    begin
        valu_controlunit_impl: valu_controlunit
        port map (
            clk => clk,
            valu_go => valu_go,
            valuop => valuop,
            vwidth => vwidth,
            source_sel => source_sel,
            carry_sel => carry_sel,
            mult_source_sel => mult_source_sel,
            mult_dest_sel => mult_dest_sel,
            reg_input_sel => reg_input_sel,
            load_lsr => load_lsr,
            load_other => load_other,
            out_valid => out_valid
        );
 
        alu_impl: vector_alu_32
            port map (
                clk => clk,
                v_in => v_in,
                w_in => w_in,
                carry_in => carry_in,
                rshift_in => rshift_in,
                carry_out => carry_out,
                valu_out => valu_out,
                valuop => valuop,
                source_sel => source_sel,
                carry_sel => carry_sel,
                mult_source_sel => mult_source_sel,
                mult_dest_sel => mult_dest_sel,
                reg_input_sel => reg_input_sel,
                load_lsr => load_lsr,
                load_other => load_other
            );
 
    process
    begin
 
            wait for 100ns;
 
            -- vadd 8_bit
            v_in <= x"FE5A3415";
            w_in <= x"3EBB6849";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "0000";
            vwidth <= "00";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
 
            assert valu_out = x"3C159C5E"
                report "vadd 8_bit : valu_out"
                severity Error;
 
            assert carry_out = '1'
                report "vadd 8_bit : carry_out"
                severity Error;
 
 
            -- vadd 16_bit
            v_in <= x"F0A17E63";
            w_in <= x"09C4A185";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "0000";
            vwidth <= "01";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
 
            assert valu_out = x"FA651FE8"
                report "vadd 16_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vadd 16_bit : carry_out"
                severity Error;
 
 
            -- vadd 32_bit
            v_in <= x"F0A17E63";
            w_in <= x"09C4A185";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "0000";
            vwidth <= "10";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = x"FA661FE8"
                report "vadd 32_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vadd 32_bit : carry_out"
                severity Error;
 
            -- vadd 64_bit
            v_in <= x"F0A17E63";
            w_in <= x"09C4A185";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "0000";
            vwidth <= "11";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = x"FA661FE9"
                report "vadd 64_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vadd 64_bit : carry_out"
                severity Error;
 
 
            -- vand 8_bit
            v_in <= "10010100110110101110010011101011";
            w_in <= "11010110101101010101010101010110";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1000";
            vwidth <= "00";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "10010100100100000100010001000010"
                report "vand 8_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vand 8_bit : carry_out"
                severity Error;
 
            -- vand 16_bit
            v_in <= "10010100110110101110010011101011";
            w_in <= "11010110101101010101010101010110";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1000";
            vwidth <= "01";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "10010100100100000100010001000010"
                report "vand 16_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vand 16_bit : carry_out"
                severity Error;
 
            -- vand 32_bit
            v_in <= "10010100110110101110010011101011";
            w_in <= "11010110101101010101010101010110";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1000";
            vwidth <= "10";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "10010100100100000100010001000010"
                report "vand 32_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vand 32_bit : carry_out"
                severity Error;
 
            -- vand 64_bit
            v_in <= "10010100110110101110010011101011";
            w_in <= "11010110101101010101010101010110";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1000";
            vwidth <= "11";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "10010100100100000100010001000010"
                report "vand 64_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vand 64_bit : carry_out"
                severity Error;
 
 
            -- vlsl 8_bit
            v_in <= "10010101001100100101101110111011";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1100";
            vwidth <= "00";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "00101010011001001011011001110110"
                report "vlsl 8_bit : valu_out"
                severity Error;
 
            assert carry_out = '1'
                report "vlsl 8_bit : carry_out"
                severity Error;
 
 
            -- vlsl 16_bit
            v_in <= "10010101001100100101101110111011";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1100";
            vwidth <= "01";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "00101010011001001011011101110110"
                report "vlsl 16_bit : valu_out"
                severity Error;
 
            assert carry_out = '1'
                report "vlsl 16_bit : carry_out"
                severity Error;
 
            -- vlsl 32_bit
            v_in <= "10010101001100100101101110111011";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1100";
            vwidth <= "10";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "00101010011001001011011101110110"
                report "vlsl 32_bit : valu_out"
                severity Error;
 
            assert carry_out = '1'
                report "vlsl 32_bit : carry_out"
                severity Error;
 
            -- vlsl 64_bit
            v_in <= "10010101001100100101101110111011";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1100";
            vwidth <= "11";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "00101010011001001011011101110111"
                report "vlsl 64_bit : valu_out"
                severity Error;
 
            assert carry_out = '1'
                report "vlsl 64_bit : carry_out"
                severity Error;
 
 
            -- vlsr 8_bit
            v_in <= "10010101001100100101101110111011";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '0';
            valuop <= "1110";
            vwidth <= "00";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "01001010000110010010110101011101"
                report "vlsr 8_bit : valu_out"
                severity Error;
 
            assert carry_out = '1'
                report "vlsr 8_bit : carry_out"
                severity Error;
 
 
            -- vlsr 16_bit
            v_in <= "10010111011010110100100110010010";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '1';
            valuop <= "1110";
            vwidth <= "01";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "01001011101101010010010011001001"
                report "vlsr 16_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vlsr 16_bit : carry_out"
                severity Error;
 
 
            -- vlsr 32_bit
            v_in <= "11001010110101011011111110110111";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '1';
            valuop <= "1110";
            vwidth <= "10";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "01100101011010101101111111011011"
                report "vlsr 32_bit : valu_out"
                severity Error;
 
            assert carry_out = '1'
                report "vlsr 32_bit : carry_out"
                severity Error;
 
            -- vlsr 64_bit
            v_in <= "00101010010110101010101001110110";
            w_in <= "11111111111111111111111111111111";
 
            carry_in <= '1';
            rshift_in <= '1';
            valuop <= "1110";
            vwidth <= "11";
 
            valu_go <= '1';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            valu_go <= '0';
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
            clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;
 
            assert valu_out = "10010101001011010101010100111011"
                report "vlsr 64_bit : valu_out"
                severity Error;
 
            assert carry_out = '0'
                report "vlsr 64_bit : carry_out"
                severity Error;
 
                        wait;
 
 
    end process;
 
end;

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[/] [hicovec/] [trunk/] [cpu/] [testbenches/] [tb_vector_alu_32.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	hmanske	`------------------------------------------------------------------`
2			`-- PROJECT: clvp (configurable lightweight vector processor)`
3			`--`
4			`-- ENTITY: tb_vector_alu_32`
5			`--`
6			`-- PURPOSE: testbench of vector_alu_32 entity`
7			`--`
8			`-- AUTHOR: harald manske, haraldmanske@gmx.de`
9			`--`
10			`-- VERSION:`
11			`-----------------------------------------------------------------`
12			`library ieee;`
13			`use ieee.std_logic_1164.all;`
14			`use ieee.std_logic_unsigned.all;`
15
16			`entity tb_vector_alu_32 is`
17			`end tb_vector_alu_32;`
18
19			`architecture testbench of tb_vector_alu_32 is`
20			`component vector_alu_32`
21			`port (`
22			`clk: in std_logic;`
23			`v_in: in std_logic_vector(31 downto 0);`
24			`w_in: in std_logic_vector(31 downto 0);`
25			`carry_in: in std_logic;`
26			`rshift_in: in std_logic;`
27			`carry_out: out std_logic;`
28			`valu_out: out std_logic_vector(31 downto 0);`
29			`valuop: in std_logic_vector(3 downto 0);`
30			`source_sel: in std_logic_vector(1 downto 0);`
31			`carry_sel: in std_logic_vector(1 downto 0);`
32			`mult_source_sel: in std_logic_vector(1 downto 0);`
33			`mult_dest_sel: in std_logic_vector(1 downto 0);`
34			`reg_input_sel: in std_logic;`
35			`load_lsr: in std_logic;`
36			`load_other: in std_logic`
37			`);`
38			`end component;`
39
40			`component valu_controlunit`
41			`port(`
42			`clk: in std_logic;`
43			`valu_go: in std_logic;`
44			`valuop: in std_logic_vector(3 downto 0);`
45			`vwidth: in std_logic_vector(1 downto 0);`
46			`source_sel: out std_logic_vector(1 downto 0);`
47			`carry_sel: out std_logic_vector(1 downto 0);`
48			`mult_source_sel: out std_logic_vector(1 downto 0);`
49			`mult_dest_sel: out std_logic_vector(1 downto 0);`
50			`reg_input_sel: out std_logic;`
51			`load_lsr: out std_logic;`
52			`load_other: out std_logic;`
53			`out_valid: out std_logic`
54			`);`
55			`end component;`
56
57			`for valu_controlunit_impl: valu_controlunit use entity work.valu_controlunit(rtl);`
58			`for alu_impl: vector_alu_32 use entity work.vector_alu_32(rtl);`
59
60			`signal clk: std_logic;`
61			`signal valu_go: std_logic;`
62			`signal vwidth: std_logic_vector(1 downto 0);`
63			`signal out_valid: std_logic;`
64			`signal v_in: std_logic_vector(31 downto 0);`
65			`signal w_in: std_logic_vector(31 downto 0);`
66			`signal carry_in: std_logic;`
67			`signal rshift_in: std_logic;`
68			`signal carry_out: std_logic;`
69			`signal valu_out: std_logic_vector(31 downto 0);`
70			`signal valuop: std_logic_vector(3 downto 0);`
71			`signal source_sel: std_logic_vector(1 downto 0);`
72			`signal carry_sel: std_logic_vector(1 downto 0);`
73			`signal load_lsr: std_logic;`
74			`signal load_other: std_logic;`
75			`signal mult_source_sel: std_logic_vector(1 downto 0);`
76			`signal mult_dest_sel: std_logic_vector(1 downto 0);`
77			`signal reg_input_sel: std_logic := '0';`
78
79			`constant period : time := 2ns;`
80
81			`begin`
82			`valu_controlunit_impl: valu_controlunit`
83			`port map (`
84			`clk => clk,`
85			`valu_go => valu_go,`
86			`valuop => valuop,`
87			`vwidth => vwidth,`
88			`source_sel => source_sel,`
89			`carry_sel => carry_sel,`
90			`mult_source_sel => mult_source_sel,`
91			`mult_dest_sel => mult_dest_sel,`
92			`reg_input_sel => reg_input_sel,`
93			`load_lsr => load_lsr,`
94			`load_other => load_other,`
95			`out_valid => out_valid`
96			`);`
97
98			`alu_impl: vector_alu_32`
99			`port map (`
100			`clk => clk,`
101			`v_in => v_in,`
102			`w_in => w_in,`
103			`carry_in => carry_in,`
104			`rshift_in => rshift_in,`
105			`carry_out => carry_out,`
106			`valu_out => valu_out,`
107			`valuop => valuop,`
108			`source_sel => source_sel,`
109			`carry_sel => carry_sel,`
110			`mult_source_sel => mult_source_sel,`
111			`mult_dest_sel => mult_dest_sel,`
112			`reg_input_sel => reg_input_sel,`
113			`load_lsr => load_lsr,`
114			`load_other => load_other`
115			`);`
116
117			`process`
118			`begin`
119
120			`wait for 100ns;`
121
122			`-- vadd 8_bit`
123			`v_in <= x"FE5A3415";`
124			`w_in <= x"3EBB6849";`
125
126			`carry_in <= '1';`
127			`rshift_in <= '0';`
128			`valuop <= "0000";`
129			`vwidth <= "00";`
130
131			`valu_go <= '1';`
132			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
133			`valu_go <= '0';`
134			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
135			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
136			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
137			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
138
139
140			`assert valu_out = x"3C159C5E"`
141			`report "vadd 8_bit : valu_out"`
142			`severity Error;`
143
144			`assert carry_out = '1'`
145			`report "vadd 8_bit : carry_out"`
146			`severity Error;`
147
148
149			`-- vadd 16_bit`
150			`v_in <= x"F0A17E63";`
151			`w_in <= x"09C4A185";`
152
153			`carry_in <= '1';`
154			`rshift_in <= '0';`
155			`valuop <= "0000";`
156			`vwidth <= "01";`
157
158			`valu_go <= '1';`
159			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
160			`valu_go <= '0';`
161			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
162			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
163			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
164			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
165
166
167			`assert valu_out = x"FA651FE8"`
168			`report "vadd 16_bit : valu_out"`
169			`severity Error;`
170
171			`assert carry_out = '0'`
172			`report "vadd 16_bit : carry_out"`
173			`severity Error;`
174
175
176			`-- vadd 32_bit`
177			`v_in <= x"F0A17E63";`
178			`w_in <= x"09C4A185";`
179
180			`carry_in <= '1';`
181			`rshift_in <= '0';`
182			`valuop <= "0000";`
183			`vwidth <= "10";`
184
185			`valu_go <= '1';`
186			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
187			`valu_go <= '0';`
188			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
189			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
190			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
191			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
192
193			`assert valu_out = x"FA661FE8"`
194			`report "vadd 32_bit : valu_out"`
195			`severity Error;`
196
197			`assert carry_out = '0'`
198			`report "vadd 32_bit : carry_out"`
199			`severity Error;`
200
201			`-- vadd 64_bit`
202			`v_in <= x"F0A17E63";`
203			`w_in <= x"09C4A185";`
204
205			`carry_in <= '1';`
206			`rshift_in <= '0';`
207			`valuop <= "0000";`
208			`vwidth <= "11";`
209
210			`valu_go <= '1';`
211			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
212			`valu_go <= '0';`
213			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
214			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
215			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
216			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
217			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
218			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
219			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
220			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
221
222			`assert valu_out = x"FA661FE9"`
223			`report "vadd 64_bit : valu_out"`
224			`severity Error;`
225
226			`assert carry_out = '0'`
227			`report "vadd 64_bit : carry_out"`
228			`severity Error;`
229
230
231			`-- vand 8_bit`
232			`v_in <= "10010100110110101110010011101011";`
233			`w_in <= "11010110101101010101010101010110";`
234
235			`carry_in <= '1';`
236			`rshift_in <= '0';`
237			`valuop <= "1000";`
238			`vwidth <= "00";`
239
240			`valu_go <= '1';`
241			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
242			`valu_go <= '0';`
243			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
244			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
245			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
246			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
247
248			`assert valu_out = "10010100100100000100010001000010"`
249			`report "vand 8_bit : valu_out"`
250			`severity Error;`
251
252			`assert carry_out = '0'`
253			`report "vand 8_bit : carry_out"`
254			`severity Error;`
255
256			`-- vand 16_bit`
257			`v_in <= "10010100110110101110010011101011";`
258			`w_in <= "11010110101101010101010101010110";`
259
260			`carry_in <= '1';`
261			`rshift_in <= '0';`
262			`valuop <= "1000";`
263			`vwidth <= "01";`
264
265			`valu_go <= '1';`
266			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
267			`valu_go <= '0';`
268			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
269			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
270			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
271			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
272
273			`assert valu_out = "10010100100100000100010001000010"`
274			`report "vand 16_bit : valu_out"`
275			`severity Error;`
276
277			`assert carry_out = '0'`
278			`report "vand 16_bit : carry_out"`
279			`severity Error;`
280
281			`-- vand 32_bit`
282			`v_in <= "10010100110110101110010011101011";`
283			`w_in <= "11010110101101010101010101010110";`
284
285			`carry_in <= '1';`
286			`rshift_in <= '0';`
287			`valuop <= "1000";`
288			`vwidth <= "10";`
289
290			`valu_go <= '1';`
291			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
292			`valu_go <= '0';`
293			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
294			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
295			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
296			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
297
298			`assert valu_out = "10010100100100000100010001000010"`
299			`report "vand 32_bit : valu_out"`
300			`severity Error;`
301
302			`assert carry_out = '0'`
303			`report "vand 32_bit : carry_out"`
304			`severity Error;`
305
306			`-- vand 64_bit`
307			`v_in <= "10010100110110101110010011101011";`
308			`w_in <= "11010110101101010101010101010110";`
309
310			`carry_in <= '1';`
311			`rshift_in <= '0';`
312			`valuop <= "1000";`
313			`vwidth <= "11";`
314
315			`valu_go <= '1';`
316			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
317			`valu_go <= '0';`
318			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
319			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
320			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
321			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
322			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
323			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
324			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
325			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
326
327			`assert valu_out = "10010100100100000100010001000010"`
328			`report "vand 64_bit : valu_out"`
329			`severity Error;`
330
331			`assert carry_out = '0'`
332			`report "vand 64_bit : carry_out"`
333			`severity Error;`
334
335
336			`-- vlsl 8_bit`
337			`v_in <= "10010101001100100101101110111011";`
338			`w_in <= "11111111111111111111111111111111";`
339
340			`carry_in <= '1';`
341			`rshift_in <= '0';`
342			`valuop <= "1100";`
343			`vwidth <= "00";`
344
345			`valu_go <= '1';`
346			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
347			`valu_go <= '0';`
348			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
349			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
350			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
351			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
352
353			`assert valu_out = "00101010011001001011011001110110"`
354			`report "vlsl 8_bit : valu_out"`
355			`severity Error;`
356
357			`assert carry_out = '1'`
358			`report "vlsl 8_bit : carry_out"`
359			`severity Error;`
360
361
362			`-- vlsl 16_bit`
363			`v_in <= "10010101001100100101101110111011";`
364			`w_in <= "11111111111111111111111111111111";`
365
366			`carry_in <= '1';`
367			`rshift_in <= '0';`
368			`valuop <= "1100";`
369			`vwidth <= "01";`
370
371			`valu_go <= '1';`
372			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
373			`valu_go <= '0';`
374			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
375			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
376			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
377			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
378
379			`assert valu_out = "00101010011001001011011101110110"`
380			`report "vlsl 16_bit : valu_out"`
381			`severity Error;`
382
383			`assert carry_out = '1'`
384			`report "vlsl 16_bit : carry_out"`
385			`severity Error;`
386
387			`-- vlsl 32_bit`
388			`v_in <= "10010101001100100101101110111011";`
389			`w_in <= "11111111111111111111111111111111";`
390
391			`carry_in <= '1';`
392			`rshift_in <= '0';`
393			`valuop <= "1100";`
394			`vwidth <= "10";`
395
396			`valu_go <= '1';`
397			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
398			`valu_go <= '0';`
399			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
400			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
401			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
402			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
403
404			`assert valu_out = "00101010011001001011011101110110"`
405			`report "vlsl 32_bit : valu_out"`
406			`severity Error;`
407
408			`assert carry_out = '1'`
409			`report "vlsl 32_bit : carry_out"`
410			`severity Error;`
411
412			`-- vlsl 64_bit`
413			`v_in <= "10010101001100100101101110111011";`
414			`w_in <= "11111111111111111111111111111111";`
415
416			`carry_in <= '1';`
417			`rshift_in <= '0';`
418			`valuop <= "1100";`
419			`vwidth <= "11";`
420
421			`valu_go <= '1';`
422			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
423			`valu_go <= '0';`
424			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
425			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
426			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
427			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
428			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
429			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
430			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
431			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
432
433			`assert valu_out = "00101010011001001011011101110111"`
434			`report "vlsl 64_bit : valu_out"`
435			`severity Error;`
436
437			`assert carry_out = '1'`
438			`report "vlsl 64_bit : carry_out"`
439			`severity Error;`
440
441
442			`-- vlsr 8_bit`
443			`v_in <= "10010101001100100101101110111011";`
444			`w_in <= "11111111111111111111111111111111";`
445
446			`carry_in <= '1';`
447			`rshift_in <= '0';`
448			`valuop <= "1110";`
449			`vwidth <= "00";`
450
451			`valu_go <= '1';`
452			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
453			`valu_go <= '0';`
454			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
455			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
456			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
457			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
458
459			`assert valu_out = "01001010000110010010110101011101"`
460			`report "vlsr 8_bit : valu_out"`
461			`severity Error;`
462
463			`assert carry_out = '1'`
464			`report "vlsr 8_bit : carry_out"`
465			`severity Error;`
466
467
468			`-- vlsr 16_bit`
469			`v_in <= "10010111011010110100100110010010";`
470			`w_in <= "11111111111111111111111111111111";`
471
472			`carry_in <= '1';`
473			`rshift_in <= '1';`
474			`valuop <= "1110";`
475			`vwidth <= "01";`
476
477			`valu_go <= '1';`
478			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
479			`valu_go <= '0';`
480			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
481			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
482			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
483			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
484
485			`assert valu_out = "01001011101101010010010011001001"`
486			`report "vlsr 16_bit : valu_out"`
487			`severity Error;`
488
489			`assert carry_out = '0'`
490			`report "vlsr 16_bit : carry_out"`
491			`severity Error;`
492
493
494			`-- vlsr 32_bit`
495			`v_in <= "11001010110101011011111110110111";`
496			`w_in <= "11111111111111111111111111111111";`
497
498			`carry_in <= '1';`
499			`rshift_in <= '1';`
500			`valuop <= "1110";`
501			`vwidth <= "10";`
502
503			`valu_go <= '1';`
504			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
505			`valu_go <= '0';`
506			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
507			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
508			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
509			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
510
511			`assert valu_out = "01100101011010101101111111011011"`
512			`report "vlsr 32_bit : valu_out"`
513			`severity Error;`
514
515			`assert carry_out = '1'`
516			`report "vlsr 32_bit : carry_out"`
517			`severity Error;`
518
519			`-- vlsr 64_bit`
520			`v_in <= "00101010010110101010101001110110";`
521			`w_in <= "11111111111111111111111111111111";`
522
523			`carry_in <= '1';`
524			`rshift_in <= '1';`
525			`valuop <= "1110";`
526			`vwidth <= "11";`
527
528			`valu_go <= '1';`
529			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
530			`valu_go <= '0';`
531			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
532			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
533			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
534			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
535			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
536			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
537			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
538			`clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2;`
539
540			`assert valu_out = "10010101001011010101010100111011"`
541			`report "vlsr 64_bit : valu_out"`
542			`severity Error;`
543
544			`assert carry_out = '0'`
545			`report "vlsr 64_bit : carry_out"`
546			`severity Error;`
547
548			`wait;`
549
550
551			`end process;`
552
553			`end;`