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------------------------------------------------------------------
-- PROJECT:      HiCoVec (highly configurable vector processor)
--
-- ENTITY:      controlunit
--
-- PURPOSE:     controlunit of scalar unit
--
-- AUTHOR:      harald manske, haraldmanske@gmx.de
--
-- VERSION:     1.0
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
 
entity controlunit is
    port(
        -- clock
        clk:            in std_logic;                       -- clock signal
 
        -- instruction in
        ir:             in std_logic_vector(31 downto 0);   -- instruction
 
        -- control signals in
        reset_cpu:      in std_logic;                       -- reset signal
        zero:           in std_logic;                       -- zero flag
        carry:          in std_logic;                       -- carry flag
        ready:          in std_logic;                       -- memory interface ready signal
 
        -- control signals out
        access_type:    out std_logic_vector(2 downto 0);   -- memory interface access type (we, oe, cs)
        c0:             out std_logic;                      -- c0 signal
        c1:             out std_logic;                      -- c1 signal
        cc2:            out std_logic_vector(1 downto 0);   -- cc2 signal
        --c3:             out std_logic;                    -- c3 signal => obsolete
        cc4:            out std_logic_vector(1 downto 0);   -- cc4 signal
        cc5:            out std_logic_vector(1 downto 0);   -- cc5 signal
        c6:             out std_logic;                      -- c6 signal
        c7:             out std_logic;                      -- c7 signal
        c8:             out std_logic;                      -- c7 signal
        load_ir:        out std_logic;                      -- instruction register load signal
        inc_ic:         out std_logic;                      -- instruction counter increment signal
        load_ic:        out std_logic;                      -- instruction counter load signal
        load_c:         out std_logic;                      -- carry flag load signal
        load_z:         out std_logic;                      -- zero flag load signal
 
        -- communication with vecor unit
        ir_ready:       out std_logic;                      -- next instruction has been loaded into ir
        s_ready:        out std_logic;                      -- data from scalar unit or mi is ready
        s_fetched:      out std_logic;                      -- signal for vector unit to continue
 
        v_ready:        in std_logic;                       -- data for scalar unit or mi is ready
        v_fetched:      in std_logic;                       -- signal for scalar unit to continue
        v_done:         in std_logic;                       -- vector unit completed command
 
        halted:         out std_logic                       -- enabled when cpu is in halt state
    );
end controlunit;
 
architecture rtl of controlunit is
    type statetype is (if1, if2, decode_wait, ld1, ld2, vld1, vld2, vld3, vld4,
        st1, st2, vst1, vst2, vst3, smv1, smv2, vms1, vms2, nop, jal, jcc, alu, flag, sync, halt,
        mova1, mova2, reset);
 
    signal state : statetype := halt;
    signal nextstate : statetype := halt;
 
begin
 
    -- state register
    process
    begin
        wait until clk='1' and clk'event;
        state <= nextstate;
 
    end process;
 
    -- state transitions
    process (state, ready, reset_cpu, ir, carry, zero, v_ready, v_fetched, v_done)
    begin
        -- avoid latches
        access_type <= "000";
        c0          <= '0';
        c1          <= '0';
        cc2         <= "00";
        cc4         <= "00";
        cc5         <= "00";
        c6          <= '0';
        c7          <= '0';
        c8          <= '0';
        load_ir     <= '0';
        inc_ic      <= '0';
        load_ic     <= '0';
        load_c      <= '0';
        load_z      <= '0';
        ir_ready    <= '0';
        s_ready     <= '0';
        s_fetched   <= '0';
        nextstate   <= reset;
        halted <= '0';
 
        if reset_cpu = '1' then
            nextstate <= reset;
        else
            case state is
                -- RESET STATE --
                when reset =>
                    cc4 <= "10";
                    cc5 <= "10";
                    load_c <= '1';
                    load_z <= '1';
                    nextstate <= if1;
 
                -- INSTRUCTION FETCH STATE 1 --
                when if1 =>
                    access_type <= "010";
                    nextstate <= if2;
 
                -- INSTRUCTION FETCH STATE 2 --
                when if2 =>
                    access_type <= "010";
                    ir_ready <= '1';
                    load_ir <= '1';
 
                    if ready = '0' then
                        nextstate <= if2;
                    else
                        nextstate <= decode_wait;
                    end if;
 
                -- DECODE AND WAIT STATE --
                when decode_wait =>
                    if ir(31 downto 28) = "1000" then       -- ld
                        if ready = '1' then
                            nextstate <= ld1;
                        else
                            nextstate <= decode_wait;
                        end if;
 
                    elsif ir(31 downto 28) = "1001" then    -- vld
                        if ready = '1' then
                            nextstate <= vld1;
                        else
                            nextstate <= decode_wait;
                        end if;
 
                    elsif ir(31 downto 28) = "1010" then    -- store
                        if ready = '1' then
                            nextstate <= st1;
                        else
                            nextstate <= decode_wait;
                        end if;
 
                    elsif ir(31 downto 26) = "101100" then   -- vst
                        if ready = '1' and v_ready = '1' then
                            nextstate <= vst1;
                        else
                            nextstate <= decode_wait;
                        end if;
 
                    elsif ir(31 downto 26) = "101101" then   -- mova
                        nextstate <= mova1;
 
                    elsif ir(31 downto 26) = "101110" then   -- mov r(t), s
                        nextstate <= smv1;
 
                    elsif ir(31 downto 26) = "101111" then   -- mov d, v(t)
                        nextstate <= vms1;
 
                    else
                        case ir(31 downto 30) is
                            when "00" =>
                                if ir(29) = '0' then                    -- nop
                                    nextstate <= nop;
 
                                elsif ir(29 downto 27) = "101" then     -- halt
                                    report "HALT";
                                    nextstate <= halt;
 
                                elsif ir(29 downto 26) = "1000" then    -- jmp, jal
                                    nextstate <= jal;
 
                                elsif ir(29 downto 28) = "11" then      -- jcc
                                    nextstate <= jcc;
                                end if;
 
                            when "01" =>                                -- alu cmd
                                nextstate <= alu;
 
                            when "11" =>                                -- set/clear flags
                                nextstate <= flag;
 
                            when others =>                              -- error
                                nextstate <= halt;
                        end case;
                    end if;
 
 
                -- LOAD STATE 1 --
                when ld1 =>
                    access_type <= "010";
                    c1 <= '1';
                    c7 <= '1';
                    nextstate <= ld2;
 
                -- LOAD STATE 2 --
                when ld2 =>
                    access_type <= "010";
                    report "LD";
                    c0 <= '1';
                    c6 <= '1';
                    c7 <= '1';
                    c8 <= '1';
                    load_z <= '1';
                    inc_ic <= '1';
 
                    if ready = '0' then
                        nextstate <= ld2;
                    else
                        nextstate <= sync;
                    end if;
 
 
                -- VECTOR LOAD STATE 1 --
                when vld1 =>
                    access_type <= "011";
                    c1 <= '1';
                    c7 <= '1';
 
                    if ready = '1' then
                        nextstate <= vld1;
                    else
                        nextstate <= vld2;
                    end if;
 
                -- VECTOR LOAD STATE 2 --
                when vld2 =>
                    access_type <= "011";
                    c1 <= '1';
                    c7 <= '1';
 
                    if ready = '1' then
                        nextstate <= vld3;
                    else
                        nextstate <= vld2;
                    end if;
 
                -- VECTOR LOAD STATE 3 --
                when vld3 =>
                    access_type <= "011";
                    c1 <= '1';
                    c7 <= '1';
                    s_ready <= '1';
 
                    if v_fetched = '1' then
                        nextstate <= vld4;
                    else
                        nextstate <= vld3;
                    end if;
 
                -- VECTOR LOAD STATE 4 --
                when vld4 =>
                    report "VLD";
                    inc_ic <= '1';
                    nextstate <= sync;
 
                -- STORE STATE 1 --
                when  st1 =>
                    access_type <= "100";
                    c1 <= '1';
                    c7 <= '1';
                    inc_ic <= '1';
 
                    nextstate <= st2;
 
                -- STORE STATE 2 --
                when  st2 =>
                    access_type <= "100";
                    c1 <= '1';
                    c7 <= '1';
 
                    if ready = '0' then
                        nextstate <= st2;
                    else
                        nextstate <= sync;
                    end if;
 
 
                -- VECTOR STORE STATE 1 --
                when vst1 =>
                    access_type <= "101";
                    c1 <= '1';
                    c7 <= '1';
 
                    if ready = '1' then
                        nextstate <= vst1;
                    else
                        nextstate <= vst2;
                    end if;
 
                -- VECTOR STORE STATE 2 --
                when vst2 =>
                    access_type <= "101";
                    c1 <= '1';
                    c7 <= '1';
 
                    if ready = '1' then
                        nextstate <= vst3;
                    else
                        nextstate <= vst2;
                    end if;
 
                 -- VECTOR STORE STATE 3 --
                when vst3 =>
                    report "VST";
                    s_fetched <= '1';
                    inc_ic <= '1';
                    nextstate <= sync;
 
                -- SCALAR MOVE TO VECTOR STATE 1 --    
                when smv1 =>
                    s_ready <= '1';
 
                    if v_fetched = '1' then
                        nextstate <= smv2;
                    else
                        nextstate <= smv1;
                    end if;
 
                -- SCALAR MOVE TO VECTOR STATE 2 --    
                when smv2 =>
                    report "MOV R(T), S";
                    inc_ic <= '1';
                    nextstate <= sync;
 
               -- MOVA STATE 1 --    
                when mova1 =>
                    s_ready <= '1';
 
                    if v_fetched = '1' then
                        nextstate <= mova2;
                    else
                        nextstate <= mova1;
                    end if;
 
                -- MOVA STATE 2 --    
                when mova2 =>
                    report "MOVA";
                    inc_ic <= '1';
                    nextstate <= sync;
 
                -- VECTOR MOVE TO SCALAR STATE  --
                when vms1 =>
                    if v_ready = '1' then
                        nextstate <= vms2;
                    else
                        nextstate <= vms1;
                    end if;
 
                -- VECTOR MOVE TO SCALAR STATE 2 --
                when vms2 =>
                    report "MOV D, V(T)";
                    cc2 <= "10";
                    c6 <= '1';
                    s_fetched <= '1';
                    inc_ic <= '1';
                    nextstate <= sync;
 
                -- NOP STATE --
                when nop =>
                    report "NOP";
                    inc_ic <= '1';
                    nextstate <= sync;
 
                -- JUMP AND LINK STATE
                when jal =>
                    report "JMP, JAL";
                    c7 <= '1';
                    load_ic <= '1';
                    cc2 <= "01";
                    c6 <= '1';
                    nextstate <= sync;
 
                -- JUMP CONDITIONAL STATE
                when jcc =>
                    report "JCC";
                    if (ir(27) = '0' and ir(26) = carry)
                      or (ir(27) = '1' and ir(26) = zero) then
                        c7 <= '1';
                        load_ic <= '1';
                    else
                        inc_ic <= '1';
                    end if;
 
                    nextstate <= sync;
 
                -- ALU COMMAND STATE --
                when alu =>
                    report "ALU COMMANDS";
                    load_c <= '1';
                    load_z <= '1';
                    c6 <= '1';
                    inc_ic <= '1';
                    nextstate <= sync;
 
                -- SET/CLEAR FLAGS STATE --
                when flag =>
                    report "SET/RESET FLAGS";
                    load_z <= ir(23);
                    load_c <= ir(22);
                    cc4 <= '1' & ir(21);
                    cc5 <= '1' & ir(20);
                    inc_ic <= '1';
                    nextstate <= sync;
 
                -- SYNC STATE --
                when  sync =>
                    if v_done = '1' then
                        nextstate <= if1;
                    else
                        nextstate <= sync;
                    end if;
 
                -- HALT STATE --
                when  halt =>
                    report "halted";
                    halted <= '1';
                    nextstate <= halt;
 
            end case;
        end if;
        end process;
end rtl;
 

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[/] [hicovec/] [trunk/] [cpu/] [units/] [controlunit.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	hmanske	`------------------------------------------------------------------`
2	4	hmanske	`-- PROJECT: HiCoVec (highly configurable vector processor)`
3	2	hmanske	`--`
4			`-- ENTITY: controlunit`
5			`--`
6			`-- PURPOSE: controlunit of scalar unit`
7			`--`
8			`-- AUTHOR: harald manske, haraldmanske@gmx.de`
9			`--`
10			`-- VERSION: 1.0`
11			`-----------------------------------------------------------------`
12			`library ieee;`
13			`use ieee.std_logic_1164.all;`
14			`use ieee.std_logic_arith.all;`
15			`use ieee.numeric_std.all;`
16
17			`entity controlunit is`
18			`port(`
19			`-- clock`
20			`clk: in std_logic; -- clock signal`
21
22			`-- instruction in`
23			`ir: in std_logic_vector(31 downto 0); -- instruction`
24
25			`-- control signals in`
26			`reset_cpu: in std_logic; -- reset signal`
27			`zero: in std_logic; -- zero flag`
28			`carry: in std_logic; -- carry flag`
29			`ready: in std_logic; -- memory interface ready signal`
30
31			`-- control signals out`
32			`access_type: out std_logic_vector(2 downto 0); -- memory interface access type (we, oe, cs)`
33			`c0: out std_logic; -- c0 signal`
34			`c1: out std_logic; -- c1 signal`
35			`cc2: out std_logic_vector(1 downto 0); -- cc2 signal`
36			`--c3: out std_logic; -- c3 signal => obsolete`
37			`cc4: out std_logic_vector(1 downto 0); -- cc4 signal`
38			`cc5: out std_logic_vector(1 downto 0); -- cc5 signal`
39			`c6: out std_logic; -- c6 signal`
40			`c7: out std_logic; -- c7 signal`
41			`c8: out std_logic; -- c7 signal`
42			`load_ir: out std_logic; -- instruction register load signal`
43			`inc_ic: out std_logic; -- instruction counter increment signal`
44			`load_ic: out std_logic; -- instruction counter load signal`
45			`load_c: out std_logic; -- carry flag load signal`
46			`load_z: out std_logic; -- zero flag load signal`
47
48			`-- communication with vecor unit`
49			`ir_ready: out std_logic; -- next instruction has been loaded into ir`
50			`s_ready: out std_logic; -- data from scalar unit or mi is ready`
51			`s_fetched: out std_logic; -- signal for vector unit to continue`
52
53			`v_ready: in std_logic; -- data for scalar unit or mi is ready`
54			`v_fetched: in std_logic; -- signal for scalar unit to continue`
55			`v_done: in std_logic; -- vector unit completed command`
56
57			`halted: out std_logic -- enabled when cpu is in halt state`
58			`);`
59			`end controlunit;`
60
61			`architecture rtl of controlunit is`
62			`type statetype is (if1, if2, decode_wait, ld1, ld2, vld1, vld2, vld3, vld4,`
63			`st1, st2, vst1, vst2, vst3, smv1, smv2, vms1, vms2, nop, jal, jcc, alu, flag, sync, halt,`
64			`mova1, mova2, reset);`
65
66			`signal state : statetype := halt;`
67			`signal nextstate : statetype := halt;`
68
69			`begin`
70
71			`-- state register`
72			`process`
73			`begin`
74			`wait until clk='1' and clk'event;`
75			`state <= nextstate;`
76
77			`end process;`
78
79			`-- state transitions`
80			`process (state, ready, reset_cpu, ir, carry, zero, v_ready, v_fetched, v_done)`
81			`begin`
82			`-- avoid latches`
83			`access_type <= "000";`
84			`c0 <= '0';`
85			`c1 <= '0';`
86			`cc2 <= "00";`
87			`cc4 <= "00";`
88			`cc5 <= "00";`
89			`c6 <= '0';`
90			`c7 <= '0';`
91			`c8 <= '0';`
92			`load_ir <= '0';`
93			`inc_ic <= '0';`
94			`load_ic <= '0';`
95			`load_c <= '0';`
96			`load_z <= '0';`
97			`ir_ready <= '0';`
98			`s_ready <= '0';`
99			`s_fetched <= '0';`
100			`nextstate <= reset;`
101			`halted <= '0';`
102
103			`if reset_cpu = '1' then`
104			`nextstate <= reset;`
105			`else`
106			`case state is`
107			`-- RESET STATE --`
108			`when reset =>`
109			`cc4 <= "10";`
110			`cc5 <= "10";`
111			`load_c <= '1';`
112			`load_z <= '1';`
113			`nextstate <= if1;`
114
115			`-- INSTRUCTION FETCH STATE 1 --`
116			`when if1 =>`
117			`access_type <= "010";`
118			`nextstate <= if2;`
119
120			`-- INSTRUCTION FETCH STATE 2 --`
121			`when if2 =>`
122			`access_type <= "010";`
123			`ir_ready <= '1';`
124			`load_ir <= '1';`
125
126			`if ready = '0' then`
127			`nextstate <= if2;`
128			`else`
129			`nextstate <= decode_wait;`
130			`end if;`
131
132			`-- DECODE AND WAIT STATE --`
133			`when decode_wait =>`
134			`if ir(31 downto 28) = "1000" then -- ld`
135			`if ready = '1' then`
136			`nextstate <= ld1;`
137			`else`
138			`nextstate <= decode_wait;`
139			`end if;`
140
141			`elsif ir(31 downto 28) = "1001" then -- vld`
142			`if ready = '1' then`
143			`nextstate <= vld1;`
144			`else`
145			`nextstate <= decode_wait;`
146			`end if;`
147
148			`elsif ir(31 downto 28) = "1010" then -- store`
149			`if ready = '1' then`
150			`nextstate <= st1;`
151			`else`
152			`nextstate <= decode_wait;`
153			`end if;`
154
155			`elsif ir(31 downto 26) = "101100" then -- vst`
156			`if ready = '1' and v_ready = '1' then`
157			`nextstate <= vst1;`
158			`else`
159			`nextstate <= decode_wait;`
160			`end if;`
161
162			`elsif ir(31 downto 26) = "101101" then -- mova`
163			`nextstate <= mova1;`
164
165			`elsif ir(31 downto 26) = "101110" then -- mov r(t), s`
166			`nextstate <= smv1;`
167
168			`elsif ir(31 downto 26) = "101111" then -- mov d, v(t)`
169			`nextstate <= vms1;`
170
171			`else`
172			`case ir(31 downto 30) is`
173			`when "00" =>`
174			`if ir(29) = '0' then -- nop`
175			`nextstate <= nop;`
176
177			`elsif ir(29 downto 27) = "101" then -- halt`
178			`report "HALT";`
179			`nextstate <= halt;`
180
181			`elsif ir(29 downto 26) = "1000" then -- jmp, jal`
182			`nextstate <= jal;`
183
184			`elsif ir(29 downto 28) = "11" then -- jcc`
185			`nextstate <= jcc;`
186			`end if;`
187
188			`when "01" => -- alu cmd`
189			`nextstate <= alu;`
190
191			`when "11" => -- set/clear flags`
192			`nextstate <= flag;`
193
194			`when others => -- error`
195			`nextstate <= halt;`
196			`end case;`
197			`end if;`
198
199
200			`-- LOAD STATE 1 --`
201			`when ld1 =>`
202			`access_type <= "010";`
203			`c1 <= '1';`
204			`c7 <= '1';`
205			`nextstate <= ld2;`
206
207			`-- LOAD STATE 2 --`
208			`when ld2 =>`
209			`access_type <= "010";`
210			`report "LD";`
211			`c0 <= '1';`
212			`c6 <= '1';`
213			`c7 <= '1';`
214			`c8 <= '1';`
215			`load_z <= '1';`
216			`inc_ic <= '1';`
217
218			`if ready = '0' then`
219			`nextstate <= ld2;`
220			`else`
221			`nextstate <= sync;`
222			`end if;`
223
224
225			`-- VECTOR LOAD STATE 1 --`
226			`when vld1 =>`
227			`access_type <= "011";`
228			`c1 <= '1';`
229			`c7 <= '1';`
230
231			`if ready = '1' then`
232			`nextstate <= vld1;`
233			`else`
234			`nextstate <= vld2;`
235			`end if;`
236
237			`-- VECTOR LOAD STATE 2 --`
238			`when vld2 =>`
239			`access_type <= "011";`
240			`c1 <= '1';`
241			`c7 <= '1';`
242
243			`if ready = '1' then`
244			`nextstate <= vld3;`
245			`else`
246			`nextstate <= vld2;`
247			`end if;`
248
249			`-- VECTOR LOAD STATE 3 --`
250			`when vld3 =>`
251			`access_type <= "011";`
252			`c1 <= '1';`
253			`c7 <= '1';`
254			`s_ready <= '1';`
255
256			`if v_fetched = '1' then`
257			`nextstate <= vld4;`
258			`else`
259			`nextstate <= vld3;`
260			`end if;`
261
262			`-- VECTOR LOAD STATE 4 --`
263			`when vld4 =>`
264			`report "VLD";`
265			`inc_ic <= '1';`
266			`nextstate <= sync;`
267
268			`-- STORE STATE 1 --`
269			`when st1 =>`
270			`access_type <= "100";`
271			`c1 <= '1';`
272			`c7 <= '1';`
273			`inc_ic <= '1';`
274
275			`nextstate <= st2;`
276
277			`-- STORE STATE 2 --`
278			`when st2 =>`
279			`access_type <= "100";`
280			`c1 <= '1';`
281			`c7 <= '1';`
282
283			`if ready = '0' then`
284			`nextstate <= st2;`
285			`else`
286			`nextstate <= sync;`
287			`end if;`
288
289
290			`-- VECTOR STORE STATE 1 --`
291			`when vst1 =>`
292			`access_type <= "101";`
293			`c1 <= '1';`
294			`c7 <= '1';`
295
296			`if ready = '1' then`
297			`nextstate <= vst1;`
298			`else`
299			`nextstate <= vst2;`
300			`end if;`
301
302			`-- VECTOR STORE STATE 2 --`
303			`when vst2 =>`
304			`access_type <= "101";`
305			`c1 <= '1';`
306			`c7 <= '1';`
307
308			`if ready = '1' then`
309			`nextstate <= vst3;`
310			`else`
311			`nextstate <= vst2;`
312			`end if;`
313
314			`-- VECTOR STORE STATE 3 --`
315			`when vst3 =>`
316			`report "VST";`
317			`s_fetched <= '1';`
318			`inc_ic <= '1';`
319			`nextstate <= sync;`
320
321			`-- SCALAR MOVE TO VECTOR STATE 1 --`
322			`when smv1 =>`
323			`s_ready <= '1';`
324
325			`if v_fetched = '1' then`
326			`nextstate <= smv2;`
327			`else`
328			`nextstate <= smv1;`
329			`end if;`
330
331			`-- SCALAR MOVE TO VECTOR STATE 2 --`
332			`when smv2 =>`
333			`report "MOV R(T), S";`
334			`inc_ic <= '1';`
335			`nextstate <= sync;`
336
337			`-- MOVA STATE 1 --`
338			`when mova1 =>`
339			`s_ready <= '1';`
340
341			`if v_fetched = '1' then`
342			`nextstate <= mova2;`
343			`else`
344			`nextstate <= mova1;`
345			`end if;`
346
347			`-- MOVA STATE 2 --`
348			`when mova2 =>`
349			`report "MOVA";`
350			`inc_ic <= '1';`
351			`nextstate <= sync;`
352
353			`-- VECTOR MOVE TO SCALAR STATE --`
354			`when vms1 =>`
355			`if v_ready = '1' then`
356			`nextstate <= vms2;`
357			`else`
358			`nextstate <= vms1;`
359			`end if;`
360
361			`-- VECTOR MOVE TO SCALAR STATE 2 --`
362			`when vms2 =>`
363			`report "MOV D, V(T)";`
364			`cc2 <= "10";`
365			`c6 <= '1';`
366			`s_fetched <= '1';`
367			`inc_ic <= '1';`
368			`nextstate <= sync;`
369
370			`-- NOP STATE --`
371			`when nop =>`
372			`report "NOP";`
373			`inc_ic <= '1';`
374			`nextstate <= sync;`
375
376			`-- JUMP AND LINK STATE`
377			`when jal =>`
378			`report "JMP, JAL";`
379			`c7 <= '1';`
380			`load_ic <= '1';`
381			`cc2 <= "01";`
382			`c6 <= '1';`
383			`nextstate <= sync;`
384
385			`-- JUMP CONDITIONAL STATE`
386			`when jcc =>`
387			`report "JCC";`
388			`if (ir(27) = '0' and ir(26) = carry)`
389			`or (ir(27) = '1' and ir(26) = zero) then`
390			`c7 <= '1';`
391			`load_ic <= '1';`
392			`else`
393			`inc_ic <= '1';`
394			`end if;`
395
396			`nextstate <= sync;`
397
398			`-- ALU COMMAND STATE --`
399			`when alu =>`
400			`report "ALU COMMANDS";`
401			`load_c <= '1';`
402			`load_z <= '1';`
403			`c6 <= '1';`
404			`inc_ic <= '1';`
405			`nextstate <= sync;`
406
407			`-- SET/CLEAR FLAGS STATE --`
408			`when flag =>`
409			`report "SET/RESET FLAGS";`
410			`load_z <= ir(23);`
411			`load_c <= ir(22);`
412			`cc4 <= '1' & ir(21);`
413			`cc5 <= '1' & ir(20);`
414			`inc_ic <= '1';`
415			`nextstate <= sync;`
416
417			`-- SYNC STATE --`
418			`when sync =>`
419			`if v_done = '1' then`
420			`nextstate <= if1;`
421			`else`
422			`nextstate <= sync;`
423			`end if;`
424
425			`-- HALT STATE --`
426			`when halt =>`
427			`report "halted";`
428			`halted <= '1';`
429			`nextstate <= halt;`
430
431			`end case;`
432			`end if;`
433			`end process;`
434			`end rtl;`
435