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[/] [hicovec/] [trunk/] [cpu/] [units/] [debugger.vhd] - Blame information for rev 5

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------------------------------------------------------------------
-- PROJECT:      HiCoVec (highly configurable vector processor)
--
-- ENTITY:      debugger
--
-- PURPOSE:     debugger for clvp
--              controls cpu via rs232
--
-- AUTHOR:      harald manske, haraldmanske@gmx.de
--
-- VERSION:     1.0
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity debugger is
    port (
        clk_in: in std_logic;           -- use 50mhz for rs232 timing
 
        clk_cpu: out std_logic;
        clk_mem: out std_logic;
 
        reset_out: out std_logic;
 
        rs232_txd: out std_logic;
        rs232_rxd: in std_logic;
 
        a: in std_logic_vector(31 downto 0);
        x: in std_logic_vector(31 downto 0);
        y: in std_logic_vector(31 downto 0);
 
        ir: in std_logic_vector(31 downto 0);
        ic: in std_logic_vector(31 downto 0);
 
        mem_switch: out std_logic;
        mem_ready: in std_logic;
 
        mem_access: in std_logic_vector(2 downto 0);
        mem_access_dbg: out std_logic_vector(2 downto 0);
 
        mem_addr: in std_logic_vector(31 downto 0);
        mem_addr_dbg: out std_logic_vector(31 downto 0);
 
        mem_data: in std_logic_vector(31 downto 0);
        mem_data_dbg: out std_logic_vector(31 downto 0);
 
        carry: in std_logic;
        zero: in std_logic;
        ir_ready: in std_logic;
        halted: in std_logic
    );
end debugger;
 
architecture rtl of debugger is
    component rs232 -- code from michael sch�ferling
        generic(         DATABITS:  integer:= 8;
                     STARTBITS: integer:= 1;
                     STOPBITS:  integer:= 1
        );
        port(   CLK_50MHZ        : in  std_logic;
                RS232_RXD        : in  std_logic;
                RS232_TXD        : out std_logic;
 
                DATA_TX          : in  std_logic_vector(DATABITS-1 downto 0);
                TX_SEND_DATA : in  std_logic;
                TX_BUSY          : out std_logic;
 
                DATA_RX          : out std_logic_vector(DATABITS-1 downto 0);
                RX_DATA_RCVD : out std_logic;
                RX_BUSY          : out std_logic
        );
    end component;
 
    component bufg
        port (
            i: in  std_logic;
            o: out std_logic
        );
    end component;
 
 
    for rs232_impl: rs232 use entity work.rs232(Behavioral);
 
    signal data_tx: std_logic_vector(7 downto 0);
    signal data_rx: std_logic_vector(7 downto 0);
    signal tx_busy: std_logic;
    signal rx_busy: std_logic;
    signal data_received: std_logic;
    signal send_data: std_logic;
 
    signal clk_buffer_cpu, clk_buffer_mem: std_logic;
 
    -- statemachine debugger
    type statetype is (waiting, decode, clock, reset1, reset2, flags, rega, regx,
                       regy, regir, regic, busy8, init8, sending8, busy32, init32, sending32, inc32, echo,
                       ma, md, go, pause, to_fetch_address, to_fetch_data, fetch_address, fetch_data, to_normal,
                       mem_read1, mem_read2, mem_read3,mem_read4, mem_write1, mem_write2, mem_write3, mem_write4,
                       mem_restore1, mem_restore2, mem_restore3, mem_restore4, send_checksum, startcc, stopcc,
                       ccstatus, getcc);
 
    signal state : statetype := waiting;
    signal nextstate : statetype := waiting;
 
    -- statemachine clock logic
    type clocktype is (high, low, freehigh, freelow, memorylow, memoryhigh, ccountstart, ccountlow, ccounthigh);
    signal clockstate : clocktype := low;
    signal nextclockstate : clocktype := low;
 
    signal counter : std_logic_vector(1 downto 0) := "00";
    signal inc: std_logic;
 
    signal clockcounter : std_logic_vector(31 downto 0) := (others => '0');
    signal clockcounter_inc, clockcounter_res : std_logic;
 
    signal in_buffer: std_logic_vector(31 downto 0);
    signal out_buffer: std_logic_vector(31 downto 0) := (others => '0');
 
    signal ar: std_logic_vector(31 downto 0) := (others => '0');
    signal ar_shift: std_logic;
 
    signal dr: std_logic_vector(31 downto 0) := (others => '0');
    signal dr_shift: std_logic;
 
    signal load, load_mem_data: std_logic;
    signal tofree, todebug, tomemory, clocktick : std_logic;
    signal startclockcount, stopclockcount, clockcountstatus : std_logic;
 
    signal status: std_logic_vector(1 downto 0) := (others => '0');
    signal st_input: std_logic_vector(1 downto 0);
    signal st_set: std_logic;
 
    signal checksum : std_logic_vector(7 downto 0);
 
begin
    rs232_impl: rs232
        generic map (DATABITS => 8, STARTBITS => 1, STOPBITS => 1)
        port map (
            CLK_50MHZ => clk_in, RS232_RXD => rs232_rxd, RS232_TXD => rs232_txd,
            DATA_TX => data_tx, TX_SEND_DATA => send_data, TX_BUSY => tx_busy,
            DATA_RX => data_rx, RX_DATA_RCVD => data_received, RX_BUSY => rx_busy
        );
 
    gbuf_for_clk_cpu: bufg
        port map (
            i => clk_buffer_cpu,
            o => clk_cpu
        );
 
    gbuf_for_clk_mem: bufg
        port map (
            i => clk_buffer_mem,
            o => clk_mem
        );
 
 
    -- counter
    process
    begin
        wait until clk_in='1' and clk_in'event;
        counter <= counter;
        clockcounter <= clockcounter;
 
        if inc = '1' then
            counter <= counter + '1';
        end if;
 
        if clockcounter_inc = '1' then
            clockcounter <= clockcounter +1;
        else
            if clockcounter_res = '1' then
                clockcounter <= (others => '0');
            end if;
        end if;
 
    end process;
 
    -- register
    process
    begin
        wait until clk_in='1' and clk_in'event;
 
        out_buffer <= out_buffer;
        status <= status;
 
        ar <= ar;
        dr <= dr;
 
 
        if load = '1' then
            out_buffer <= in_buffer;
        else
            if load_mem_data = '1' then
                out_buffer <= mem_data;
            end if;
        end if;
 
        if ar_shift = '1' then
            ar(31 downto 8) <= ar(23 downto 0);
            ar(7 downto 0) <= data_rx;
        end if;
 
        if dr_shift = '1' then
            dr(31 downto 8) <= dr(23 downto 0);
            dr(7 downto 0) <= data_rx;
        end if;
 
        if st_set = '1' then
            status <= st_input;
        end if;
 
    end process;
 
    mem_addr_dbg <= ar;
    mem_data_dbg <= dr;
    checksum <= out_buffer(31 downto 24) xor out_buffer(23 downto 16)
                xor out_buffer(15 downto 8) xor out_buffer(7 downto 0);
 
    -- state register
    process
    begin
        wait until clk_in='1' and clk_in'event;
        state <= nextstate;
        clockstate <= nextclockstate;
 
    end process;
 
    -- clock state machine
    process (clockstate, tofree, todebug, tomemory, clocktick, clockcounter_inc, clockcounter_res, clockcounter, ic,
             startclockcount, stopclockcount, ar)
    begin
        -- avoid latches
        clk_buffer_cpu <= '0';
        clk_buffer_mem <= '0';
        clockcountstatus <= '1';
        clockcounter_inc <= '0';
        clockcounter_res <= '0';
 
        case clockstate is
            -- CLOCK COUNTING STATES --
            when ccountstart =>             -- start clock counting
                clockcounter_inc <= '0';
                clockcounter_res <= '1';
                clockcountstatus <= '0';
                nextclockstate <= ccountlow;
 
            when ccountlow =>               -- generate clock low signal
                clockcountstatus <= '0';
                clk_buffer_cpu <= '0';
                clk_buffer_mem <= '0';
 
                if stopclockcount = '1' then
                    nextclockstate <= low;
                else
                    if ic = ar then -- stop when instruction counter value matches given address
                        nextclockstate <= low;
                    else
                        nextclockstate <= ccounthigh;
                    end if;
                end if;
 
 
            when ccounthigh =>              -- generate clock high signal
                clockcountstatus <= '0';
                clockcounter_inc <= '1';
                clk_buffer_cpu <= '1';
                clk_buffer_mem <= '1';
 
                if stopclockcount = '1' then
                    nextclockstate <= low;
                else
                    nextclockstate <= ccountlow;
                end if;
 
            -- DEBUG MODE STATES --
            when low =>                     -- generate clock low signal
                clk_buffer_cpu <= '0';
                clk_buffer_mem <= '0';
 
                 if startclockcount = '1' then -- only allow to start clockcount from debug mode
                    nextclockstate <= ccountstart;
                 else
                    if tomemory = '1' then
                        nextclockstate <= memorylow;
                    else
                        if tofree = '1' then
                            nextclockstate <= freelow;
                        else
                            if clocktick = '1' then
                                nextclockstate <= high;
                            else
                                nextclockstate <= low;
                            end if;
                        end if;
                    end if;
                 end if;
 
            when high =>                    -- generate clock high signal
                clk_buffer_cpu <= '1';
                clk_buffer_mem <= '1';
 
                if tomemory = '1' then
                    nextclockstate <= memorylow;
                else
                    if tofree = '1' then
                        nextclockstate <= freelow;
                    else
                        nextclockstate <= low;
                    end if;
                end if;
 
 
            -- FREE RUNNING MODE STATES --
            when freelow =>                 -- generate clock low signal
                clk_buffer_cpu <= '0';
                clk_buffer_mem <= '0';
 
                if tomemory = '1' then
                    nextclockstate <= memorylow;
                else
                    if todebug = '1' then
                        nextclockstate <= low;
                    else
                        nextclockstate <= freehigh;
                    end if;
                end if;
 
 
            when freehigh =>                -- generate clock high signal
                clk_buffer_cpu <= '1';
                clk_buffer_mem <= '1';
 
                if tomemory = '1' then
                    nextclockstate <= memorylow;
                else
                    if todebug = '1' then
                        nextclockstate <= low;
                    else
                        nextclockstate <= freelow;
                    end if;
                end if;
 
 
            -- CLOCK MEMORY ONLY STATES --
            when memorylow =>               -- generate memory clock low signal
                clk_buffer_mem <= '0';
 
                if todebug = '1' then
                    nextclockstate <= low;
                else
                    nextclockstate <= memoryhigh;
                end if;
 
            when memoryhigh =>              -- generate memory clock high signal
                clk_buffer_mem <= '1';
 
                if todebug = '1' then
                    nextclockstate <= low;
                else
                    nextclockstate <= memorylow;
                end if;
 
        end case;
    end process;
 
    -- debugger state machine
    process (clk_in, data_rx, a, x, y, ir, ic, carry, zero, ir_ready, tx_busy, data_received, counter,
             state, out_buffer, mem_addr, mem_data, mem_access, mem_ready, halted, status, checksum,
             clockcountstatus, clockcounter )
    begin
        -- avoid latches 
        reset_out <= '0';
        send_data <= '0';
        data_tx <= (others => '0');
        in_buffer <= (others => '0');
        nextstate <= waiting;
        inc <= '0';
        load <= '0';
 
        tofree <= '0';
        todebug <= '0';
        tomemory <= '0';
        clocktick <= '0';
 
        ar_shift <= '0';
        dr_shift <= '0';
 
        st_input <= (others => '0');
        st_set <= '0';
 
        mem_switch <= '0';
        mem_access_dbg <= "000";
        load_mem_data <= '0';
 
        startclockcount <= '0';
        stopclockcount <= '0';
 
        case state is
            -- WAIT FOR COMMANDS / DATA --
            when waiting =>
                if data_received = '1' then
                    nextstate <= decode;
                else
                    nextstate <= waiting;
                end if;
 
            -- DECODE STATE --
            when decode =>
                case status is
                    when "00" =>  -- normal modus
                        case data_rx is
                            when "01100011" | "01000011" => -- c/C = clock
                                nextstate <= clock;
 
                            when "01110010" | "01010010" => -- r/R = reset
                                nextstate <= reset1;
 
                            when "01100110" | "01000110" => -- f/F = flags
                                nextstate <= flags;
 
                            when "01100001" | "01000001" => -- a/A = register a
                                nextstate <= rega;
 
                            when "01111000" | "01011000" => -- x/X = register x
                                nextstate <= regx;
 
                            when "01111001" | "01011001" => -- y/Y = register y
                                nextstate <= regy;
 
                            when "01101001" | "01001001" => -- i/I = instruction register
                                nextstate <= regir;
 
                            when "01101010" | "01001010" => -- j/J = instruction counter
                                nextstate <= regic;
 
                            when "01101101" | "01001101" => -- m/M = memory data
                                nextstate <= md;
 
                            when "01101110" | "01001110" => -- n/N = memory address
                                nextstate <= ma;
 
                            when "01100111" | "01000111" => -- g/G = enter free-running-mode
                                nextstate <= go;
 
                            when "01110000" | "01010000" => -- p/P = leave free-running-mode
                                nextstate <= pause;
 
                            when "00110000" =>              -- 0 = fetch address
                                nextstate <= to_fetch_address;
 
                            when "00110001" =>              -- 1 = fetch data
                                nextstate <= to_fetch_data;
 
                            when "00110010" =>              -- 2 = read from memory
                                nextstate <= mem_read1;
 
                            when "00110011" =>              -- 3 = write to memory
                                nextstate <= mem_write1;
 
                            when "00110100" =>              -- 4 = enter clock count mode
                                nextstate <= startcc;
 
                            when "00110101" =>              -- 5 = stop clock count mode
                                nextstate <= stopcc;
 
                            when "00110110" =>              -- 6 = clock count status
                                nextstate <= ccstatus;
 
                            when "00110111" =>              -- 7 = get clock counter
                                nextstate <= getcc;
 
                            when others =>                  -- unknown command, echo
                                nextstate <= echo;
                        end case;
 
                    when "01" =>  -- receiving memory write command
                        nextstate <= fetch_address;
 
                    when "10" =>  -- receiving memory read command
                        nextstate <= fetch_data;
 
                    when others =>
                        nextstate <= to_normal;
 
                end case;
 
            -- CLOCKCOUNTER STATS --
            when startcc =>                     -- start clock counter
                startclockcount <= '1';
                nextstate <= echo;
 
            when stopcc =>                      -- stop clock counter
                stopclockcount <= '1';
                nextstate <= echo;
 
            when ccstatus =>                    -- get status of clock counter
                in_buffer(7 downto 1) <= (others => '0');
                in_buffer(0) <= clockcountstatus;
                load <= '1';
                nextstate <= busy8;
 
            when getcc =>                       -- get clockcounter value
                in_buffer(31 downto 0) <= clockcounter;
                load <= '1';
                nextstate <= busy32;
 
 
            -- READ MEMORY STATES --
            when mem_read1 =>                   -- complete operation from cpu
                tomemory <= '1';
                if mem_ready = '0' then
                    nextstate <= mem_read1;
                else
                    nextstate <= mem_read2;
                end if;
 
            when mem_read2 =>                   -- switch from cpu to debugger control
                mem_switch <= '1';
                nextstate <= mem_read3;
 
            when mem_read3 =>                   -- start operation
                mem_switch <= '1';
                mem_access_dbg <= "010";
 
                if mem_ready = '1' then
                    nextstate <= mem_read3;
                else
                    nextstate <= mem_read4;
                end if;
 
            when mem_read4 =>                   -- finish operation
                mem_switch <= '1';
                mem_access_dbg <= "010";
 
                load_mem_data <= '1';
 
                if mem_ready = '1' then
                    nextstate <= mem_restore1;
                else
                    nextstate <= mem_read4;
                end if;
 
 
            -- WRITE MEMORY STATES --
            when mem_write1 =>                   -- complete operation from cpu
                tomemory <= '1';
 
                if mem_ready = '0' then
                    nextstate <= mem_write1;
                else
                    nextstate <= mem_write2;
                end if;
 
            when mem_write2 =>                  -- switch from cpu to debugger control
                mem_switch <= '1';
                nextstate <= mem_write3;
 
 
            when mem_write3 =>                  -- start operation
                mem_switch <= '1';
                mem_access_dbg <= "100";
 
                if mem_ready = '0' then
                    nextstate <= mem_write4;
                else
                    nextstate <= mem_write3;
                end if;
 
            when mem_write4 =>                  -- finish operation
                mem_switch <= '1';
                mem_access_dbg <= "100";
 
                if mem_ready = '1' then
                    nextstate <= mem_restore1;
                else
                    nextstate <= mem_write4;
                end if;
 
 
            --  RESTORE PREVIOUS MEMORY STATES --
            when mem_restore1 =>                -- switch from debugger to cpu control
                mem_switch <= '1';
                nextstate <= mem_restore2;
 
            when mem_restore2 =>
                nextstate <= mem_restore3;
 
            when mem_restore3 =>                -- wait for completition
                if mem_ready = '0' then
                    nextstate <= mem_restore3;
                else
                    nextstate <= mem_restore4;
                end if;
 
            when mem_restore4 =>                -- send back answer via rs232
                todebug <= '1';
 
                if data_rx = "00110010" then
                    nextstate <= busy32;  -- read (send 32 bit data back)
                else
                    nextstate <= echo;  -- write (send ok back)      
                end if;
 
 
            -- FETCH ADDRESS VALUE --
            when fetch_address =>
                inc <= '1';
                ar_shift <= '1';
 
                if counter = "11" then
                    nextstate <= to_normal;
                else
                    nextstate <= echo;
                end if;
 
            -- FETCH DATA VALUE --
            when fetch_data =>
                inc <= '1';
                dr_shift <= '1';
 
                if counter = "11" then
                    nextstate <= to_normal;
                else
                    nextstate <= echo;
                end if;
 
            -- SWITCH TO FETCH ADDRESS MODE --
            when to_fetch_address =>
                st_input <= "01";
                st_set <= '1';
                nextstate <= echo;
 
            -- SWITCH TO FETCH DATA MODE --
            when to_fetch_data =>
                st_input <= "10";
                st_set <= '1';
                nextstate <= echo;
 
            -- SWITCH TO NORMAL ADDRESS MODE --
            when to_normal =>
                st_input <= "00";
                st_set <= '1';
                nextstate <= echo;
 
            -- SWITCH OT FREE RUNNING MODE --
            when go =>
                tofree <= '1';
                nextstate <= echo;
 
            -- END FREE RUNNING MODE --
            when pause =>
                todebug <= '1';
                nextstate <= echo;
 
                        -- GENERATE ONE CLOCKTICK --
            when clock =>
                clocktick <= '1';
                nextstate <= echo;
 
            -- RESET CPU --
            when reset1 =>
                reset_out <= '1';
                clocktick <= '1';
                nextstate <= reset2;
 
            when reset2 =>
                reset_out <= '1';
                nextstate <= echo;
 
            -- SEND FLAGS --
            when flags =>
                in_buffer(7 downto 0) <= ir_ready & mem_ready & mem_access & halted & zero & carry;
                load <= '1';
                nextstate <= busy8;
 
            -- SEND AKKUMULATOR --
            when rega =>
                in_buffer(31 downto 0) <= a;
                load <= '1';
                nextstate <= busy32;
 
            -- SEND REGISTER X --
            when regx =>
                in_buffer(31 downto 0) <= x;
                load <= '1';
                nextstate <= busy32;
 
            -- SEND REGISTER > --
            when regy =>
                in_buffer(31 downto 0) <= y;
                load <= '1';
                nextstate <= busy32;
 
            -- SEND INSTRUCTION REGISTER --
            when regir =>
                in_buffer(31 downto 0) <= ir;
                load <= '1';
                nextstate <= busy32;
 
            -- SEND INSTRUCTION COUNTER --
            when regic =>
                in_buffer(31 downto 0) <= ic;
                load <= '1';
                nextstate <= busy32;
 
            -- SEND MEMORY ADDRESS -- 
            when ma =>
                in_buffer(31 downto 0) <= mem_addr;
                load <= '1';
                nextstate <= busy32;
 
            -- SEND MEMORY DATA --
            when md =>
                in_buffer(31 downto 0) <= mem_data;
                load <= '1';
                nextstate <= busy32;
 
            -- SEND RECEIVED COMMAND BACK --
            when echo =>
                in_buffer(7 downto 0) <= data_rx;
                load <= '1';
                nextstate <= busy8;
 
 
            -- COMMON SENDING ROUTINES --
            when busy8 =>
                if tx_busy = '0' then
                    nextstate <= init8;
                else
                    nextstate <= busy8;
                end if;
 
            when init8 =>
                data_tx <= out_buffer(7 downto 0);
                send_data <= '1';
 
                if tx_busy = '1' then
                    nextstate <= sending8;
                else
                    nextstate <= init8;
                end if;
 
            when sending8 =>
                if tx_busy = '0' then
                    nextstate <= waiting;
                else
                    nextstate <= sending8;
                end if;
 
            when busy32 =>
                if tx_busy = '0' then
                    nextstate <= init32;
                else
                    nextstate <= busy32;
                end if;
 
            when init32 =>
                case counter is
                    when "00" =>
                        data_tx <= out_buffer(7 downto 0);
                    when "01" =>
                        data_tx <= out_buffer(15 downto 8);
                    when "10" =>
                        data_tx <= out_buffer(23 downto 16);
                    when "11" =>
                        data_tx <= out_buffer(31 downto 24);
                    when others =>
                        data_tx <= (others => '0');
                end case;
 
                send_data <= '1';
 
                if tx_busy = '1' then
                    nextstate <= sending32;
                else
                    nextstate <= init32;
                end if;
 
            when sending32 =>
                if tx_busy = '0' then
                    nextstate <= inc32;
                else
                    nextstate <= sending32;
                end if;
 
            when inc32 =>
                inc <= '1';
 
                if counter = "11" then
                    nextstate <= send_checksum;
                else
                    nextstate <= busy32;
                end if;
 
            -- send checksum for 32 bit data
            when send_checksum =>
                data_tx <= checksum;
                send_data <= '1';
 
                if tx_busy = '1' then
                    nextstate <= sending8;
                else
                    nextstate <= send_checksum;
                end if;
 
        end case;
    end process;
end rtl;

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[/] [hicovec/] [trunk/] [cpu/] [units/] [debugger.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	hmanske	`------------------------------------------------------------------`
2	4	hmanske	`-- PROJECT: HiCoVec (highly configurable vector processor)`
3	2	hmanske	`--`
4			`-- ENTITY: debugger`
5			`--`
6			`-- PURPOSE: debugger for clvp`
7			`-- controls cpu via rs232`
8			`--`
9			`-- AUTHOR: harald manske, haraldmanske@gmx.de`
10			`--`
11			`-- VERSION: 1.0`
12			`-----------------------------------------------------------------`
13			`library ieee;`
14			`use ieee.std_logic_1164.all;`
15			`use ieee.std_logic_unsigned.all;`
16
17			`entity debugger is`
18			`port (`
19			`clk_in: in std_logic; -- use 50mhz for rs232 timing`
20
21			`clk_cpu: out std_logic;`
22			`clk_mem: out std_logic;`
23
24			`reset_out: out std_logic;`
25
26			`rs232_txd: out std_logic;`
27			`rs232_rxd: in std_logic;`
28
29			`a: in std_logic_vector(31 downto 0);`
30			`x: in std_logic_vector(31 downto 0);`
31			`y: in std_logic_vector(31 downto 0);`
32
33			`ir: in std_logic_vector(31 downto 0);`
34			`ic: in std_logic_vector(31 downto 0);`
35
36			`mem_switch: out std_logic;`
37			`mem_ready: in std_logic;`
38
39			`mem_access: in std_logic_vector(2 downto 0);`
40			`mem_access_dbg: out std_logic_vector(2 downto 0);`
41
42			`mem_addr: in std_logic_vector(31 downto 0);`
43			`mem_addr_dbg: out std_logic_vector(31 downto 0);`
44
45			`mem_data: in std_logic_vector(31 downto 0);`
46			`mem_data_dbg: out std_logic_vector(31 downto 0);`
47
48			`carry: in std_logic;`
49			`zero: in std_logic;`
50			`ir_ready: in std_logic;`
51			`halted: in std_logic`
52			`);`
53			`end debugger;`
54
55			`architecture rtl of debugger is`
56			`component rs232 -- code from michael sch�ferling`
57			`generic( DATABITS: integer:= 8;`
58			`STARTBITS: integer:= 1;`
59			`STOPBITS: integer:= 1`
60			`);`
61			`port( CLK_50MHZ : in std_logic;`
62			`RS232_RXD : in std_logic;`
63			`RS232_TXD : out std_logic;`
64
65			`DATA_TX : in std_logic_vector(DATABITS-1 downto 0);`
66			`TX_SEND_DATA : in std_logic;`
67			`TX_BUSY : out std_logic;`
68
69			`DATA_RX : out std_logic_vector(DATABITS-1 downto 0);`
70			`RX_DATA_RCVD : out std_logic;`
71			`RX_BUSY : out std_logic`
72			`);`
73			`end component;`
74
75			`component bufg`
76			`port (`
77			`i: in std_logic;`
78			`o: out std_logic`
79			`);`
80			`end component;`
81
82
83			`for rs232_impl: rs232 use entity work.rs232(Behavioral);`
84
85			`signal data_tx: std_logic_vector(7 downto 0);`
86			`signal data_rx: std_logic_vector(7 downto 0);`
87			`signal tx_busy: std_logic;`
88			`signal rx_busy: std_logic;`
89			`signal data_received: std_logic;`
90			`signal send_data: std_logic;`
91
92			`signal clk_buffer_cpu, clk_buffer_mem: std_logic;`
93
94			`-- statemachine debugger`
95			`type statetype is (waiting, decode, clock, reset1, reset2, flags, rega, regx,`
96			`regy, regir, regic, busy8, init8, sending8, busy32, init32, sending32, inc32, echo,`
97			`ma, md, go, pause, to_fetch_address, to_fetch_data, fetch_address, fetch_data, to_normal,`
98			`mem_read1, mem_read2, mem_read3,mem_read4, mem_write1, mem_write2, mem_write3, mem_write4,`
99			`mem_restore1, mem_restore2, mem_restore3, mem_restore4, send_checksum, startcc, stopcc,`
100			`ccstatus, getcc);`
101
102			`signal state : statetype := waiting;`
103			`signal nextstate : statetype := waiting;`
104
105			`-- statemachine clock logic`
106			`type clocktype is (high, low, freehigh, freelow, memorylow, memoryhigh, ccountstart, ccountlow, ccounthigh);`
107			`signal clockstate : clocktype := low;`
108			`signal nextclockstate : clocktype := low;`
109
110			`signal counter : std_logic_vector(1 downto 0) := "00";`
111			`signal inc: std_logic;`
112
113			`signal clockcounter : std_logic_vector(31 downto 0) := (others => '0');`
114			`signal clockcounter_inc, clockcounter_res : std_logic;`
115
116			`signal in_buffer: std_logic_vector(31 downto 0);`
117			`signal out_buffer: std_logic_vector(31 downto 0) := (others => '0');`
118
119			`signal ar: std_logic_vector(31 downto 0) := (others => '0');`
120			`signal ar_shift: std_logic;`
121
122			`signal dr: std_logic_vector(31 downto 0) := (others => '0');`
123			`signal dr_shift: std_logic;`
124
125			`signal load, load_mem_data: std_logic;`
126			`signal tofree, todebug, tomemory, clocktick : std_logic;`
127			`signal startclockcount, stopclockcount, clockcountstatus : std_logic;`
128
129			`signal status: std_logic_vector(1 downto 0) := (others => '0');`
130			`signal st_input: std_logic_vector(1 downto 0);`
131			`signal st_set: std_logic;`
132
133			`signal checksum : std_logic_vector(7 downto 0);`
134
135			`begin`
136			`rs232_impl: rs232`
137			`generic map (DATABITS => 8, STARTBITS => 1, STOPBITS => 1)`
138			`port map (`
139			`CLK_50MHZ => clk_in, RS232_RXD => rs232_rxd, RS232_TXD => rs232_txd,`
140			`DATA_TX => data_tx, TX_SEND_DATA => send_data, TX_BUSY => tx_busy,`
141			`DATA_RX => data_rx, RX_DATA_RCVD => data_received, RX_BUSY => rx_busy`
142			`);`
143
144			`gbuf_for_clk_cpu: bufg`
145			`port map (`
146			`i => clk_buffer_cpu,`
147			`o => clk_cpu`
148			`);`
149
150			`gbuf_for_clk_mem: bufg`
151			`port map (`
152			`i => clk_buffer_mem,`
153			`o => clk_mem`
154			`);`
155
156
157			`-- counter`
158			`process`
159			`begin`
160			`wait until clk_in='1' and clk_in'event;`
161			`counter <= counter;`
162			`clockcounter <= clockcounter;`
163
164			`if inc = '1' then`
165			`counter <= counter + '1';`
166			`end if;`
167
168			`if clockcounter_inc = '1' then`
169			`clockcounter <= clockcounter +1;`
170			`else`
171			`if clockcounter_res = '1' then`
172			`clockcounter <= (others => '0');`
173			`end if;`
174			`end if;`
175
176			`end process;`
177
178			`-- register`
179			`process`
180			`begin`
181			`wait until clk_in='1' and clk_in'event;`
182
183			`out_buffer <= out_buffer;`
184			`status <= status;`
185
186			`ar <= ar;`
187			`dr <= dr;`
188
189
190			`if load = '1' then`
191			`out_buffer <= in_buffer;`
192			`else`
193			`if load_mem_data = '1' then`
194			`out_buffer <= mem_data;`
195			`end if;`
196			`end if;`
197
198			`if ar_shift = '1' then`
199			`ar(31 downto 8) <= ar(23 downto 0);`
200			`ar(7 downto 0) <= data_rx;`
201			`end if;`
202
203			`if dr_shift = '1' then`
204			`dr(31 downto 8) <= dr(23 downto 0);`
205			`dr(7 downto 0) <= data_rx;`
206			`end if;`
207
208			`if st_set = '1' then`
209			`status <= st_input;`
210			`end if;`
211
212			`end process;`
213
214			`mem_addr_dbg <= ar;`
215			`mem_data_dbg <= dr;`
216			`checksum <= out_buffer(31 downto 24) xor out_buffer(23 downto 16)`
217			`xor out_buffer(15 downto 8) xor out_buffer(7 downto 0);`
218
219			`-- state register`
220			`process`
221			`begin`
222			`wait until clk_in='1' and clk_in'event;`
223			`state <= nextstate;`
224			`clockstate <= nextclockstate;`
225
226			`end process;`
227
228			`-- clock state machine`
229			`process (clockstate, tofree, todebug, tomemory, clocktick, clockcounter_inc, clockcounter_res, clockcounter, ic,`
230			`startclockcount, stopclockcount, ar)`
231			`begin`
232			`-- avoid latches`
233			`clk_buffer_cpu <= '0';`
234			`clk_buffer_mem <= '0';`
235			`clockcountstatus <= '1';`
236			`clockcounter_inc <= '0';`
237			`clockcounter_res <= '0';`
238
239			`case clockstate is`
240			`-- CLOCK COUNTING STATES --`
241			`when ccountstart => -- start clock counting`
242			`clockcounter_inc <= '0';`
243			`clockcounter_res <= '1';`
244			`clockcountstatus <= '0';`
245			`nextclockstate <= ccountlow;`
246
247			`when ccountlow => -- generate clock low signal`
248			`clockcountstatus <= '0';`
249			`clk_buffer_cpu <= '0';`
250			`clk_buffer_mem <= '0';`
251
252			`if stopclockcount = '1' then`
253			`nextclockstate <= low;`
254			`else`
255			`if ic = ar then -- stop when instruction counter value matches given address`
256			`nextclockstate <= low;`
257			`else`
258			`nextclockstate <= ccounthigh;`
259			`end if;`
260			`end if;`
261
262
263			`when ccounthigh => -- generate clock high signal`
264			`clockcountstatus <= '0';`
265			`clockcounter_inc <= '1';`
266			`clk_buffer_cpu <= '1';`
267			`clk_buffer_mem <= '1';`
268
269			`if stopclockcount = '1' then`
270			`nextclockstate <= low;`
271			`else`
272			`nextclockstate <= ccountlow;`
273			`end if;`
274
275			`-- DEBUG MODE STATES --`
276			`when low => -- generate clock low signal`
277			`clk_buffer_cpu <= '0';`
278			`clk_buffer_mem <= '0';`
279
280			`if startclockcount = '1' then -- only allow to start clockcount from debug mode`
281			`nextclockstate <= ccountstart;`
282			`else`
283			`if tomemory = '1' then`
284			`nextclockstate <= memorylow;`
285			`else`
286			`if tofree = '1' then`
287			`nextclockstate <= freelow;`
288			`else`
289			`if clocktick = '1' then`
290			`nextclockstate <= high;`
291			`else`
292			`nextclockstate <= low;`
293			`end if;`
294			`end if;`
295			`end if;`
296			`end if;`
297
298			`when high => -- generate clock high signal`
299			`clk_buffer_cpu <= '1';`
300			`clk_buffer_mem <= '1';`
301
302			`if tomemory = '1' then`
303			`nextclockstate <= memorylow;`
304			`else`
305			`if tofree = '1' then`
306			`nextclockstate <= freelow;`
307			`else`
308			`nextclockstate <= low;`
309			`end if;`
310			`end if;`
311
312
313			`-- FREE RUNNING MODE STATES --`
314			`when freelow => -- generate clock low signal`
315			`clk_buffer_cpu <= '0';`
316			`clk_buffer_mem <= '0';`
317
318			`if tomemory = '1' then`
319			`nextclockstate <= memorylow;`
320			`else`
321			`if todebug = '1' then`
322			`nextclockstate <= low;`
323			`else`
324			`nextclockstate <= freehigh;`
325			`end if;`
326			`end if;`
327
328
329			`when freehigh => -- generate clock high signal`
330			`clk_buffer_cpu <= '1';`
331			`clk_buffer_mem <= '1';`
332
333			`if tomemory = '1' then`
334			`nextclockstate <= memorylow;`
335			`else`
336			`if todebug = '1' then`
337			`nextclockstate <= low;`
338			`else`
339			`nextclockstate <= freelow;`
340			`end if;`
341			`end if;`
342
343
344			`-- CLOCK MEMORY ONLY STATES --`
345			`when memorylow => -- generate memory clock low signal`
346			`clk_buffer_mem <= '0';`
347
348			`if todebug = '1' then`
349			`nextclockstate <= low;`
350			`else`
351			`nextclockstate <= memoryhigh;`
352			`end if;`
353
354			`when memoryhigh => -- generate memory clock high signal`
355			`clk_buffer_mem <= '1';`
356
357			`if todebug = '1' then`
358			`nextclockstate <= low;`
359			`else`
360			`nextclockstate <= memorylow;`
361			`end if;`
362
363			`end case;`
364			`end process;`
365
366			`-- debugger state machine`
367			`process (clk_in, data_rx, a, x, y, ir, ic, carry, zero, ir_ready, tx_busy, data_received, counter,`
368			`state, out_buffer, mem_addr, mem_data, mem_access, mem_ready, halted, status, checksum,`
369			`clockcountstatus, clockcounter )`
370			`begin`
371			`-- avoid latches`
372			`reset_out <= '0';`
373			`send_data <= '0';`
374			`data_tx <= (others => '0');`
375			`in_buffer <= (others => '0');`
376			`nextstate <= waiting;`
377			`inc <= '0';`
378			`load <= '0';`
379
380			`tofree <= '0';`
381			`todebug <= '0';`
382			`tomemory <= '0';`
383			`clocktick <= '0';`
384
385			`ar_shift <= '0';`
386			`dr_shift <= '0';`
387
388			`st_input <= (others => '0');`
389			`st_set <= '0';`
390
391			`mem_switch <= '0';`
392			`mem_access_dbg <= "000";`
393			`load_mem_data <= '0';`
394
395			`startclockcount <= '0';`
396			`stopclockcount <= '0';`
397
398			`case state is`
399			`-- WAIT FOR COMMANDS / DATA --`
400			`when waiting =>`
401			`if data_received = '1' then`
402			`nextstate <= decode;`
403			`else`
404			`nextstate <= waiting;`
405			`end if;`
406
407			`-- DECODE STATE --`
408			`when decode =>`
409			`case status is`
410			`when "00" => -- normal modus`
411			`case data_rx is`
412			`when "01100011" \| "01000011" => -- c/C = clock`
413			`nextstate <= clock;`
414
415			`when "01110010" \| "01010010" => -- r/R = reset`
416			`nextstate <= reset1;`
417
418			`when "01100110" \| "01000110" => -- f/F = flags`
419			`nextstate <= flags;`
420
421			`when "01100001" \| "01000001" => -- a/A = register a`
422			`nextstate <= rega;`
423
424			`when "01111000" \| "01011000" => -- x/X = register x`
425			`nextstate <= regx;`
426
427			`when "01111001" \| "01011001" => -- y/Y = register y`
428			`nextstate <= regy;`
429
430			`when "01101001" \| "01001001" => -- i/I = instruction register`
431			`nextstate <= regir;`
432
433			`when "01101010" \| "01001010" => -- j/J = instruction counter`
434			`nextstate <= regic;`
435
436			`when "01101101" \| "01001101" => -- m/M = memory data`
437			`nextstate <= md;`
438
439			`when "01101110" \| "01001110" => -- n/N = memory address`
440			`nextstate <= ma;`
441
442			`when "01100111" \| "01000111" => -- g/G = enter free-running-mode`
443			`nextstate <= go;`
444
445			`when "01110000" \| "01010000" => -- p/P = leave free-running-mode`
446			`nextstate <= pause;`
447
448			`when "00110000" => -- 0 = fetch address`
449			`nextstate <= to_fetch_address;`
450
451			`when "00110001" => -- 1 = fetch data`
452			`nextstate <= to_fetch_data;`
453
454			`when "00110010" => -- 2 = read from memory`
455			`nextstate <= mem_read1;`
456
457			`when "00110011" => -- 3 = write to memory`
458			`nextstate <= mem_write1;`
459
460			`when "00110100" => -- 4 = enter clock count mode`
461			`nextstate <= startcc;`
462
463			`when "00110101" => -- 5 = stop clock count mode`
464			`nextstate <= stopcc;`
465
466			`when "00110110" => -- 6 = clock count status`
467			`nextstate <= ccstatus;`
468
469			`when "00110111" => -- 7 = get clock counter`
470			`nextstate <= getcc;`
471
472			`when others => -- unknown command, echo`
473			`nextstate <= echo;`
474			`end case;`
475
476			`when "01" => -- receiving memory write command`
477			`nextstate <= fetch_address;`
478
479			`when "10" => -- receiving memory read command`
480			`nextstate <= fetch_data;`
481
482			`when others =>`
483			`nextstate <= to_normal;`
484
485			`end case;`
486
487			`-- CLOCKCOUNTER STATS --`
488			`when startcc => -- start clock counter`
489			`startclockcount <= '1';`
490			`nextstate <= echo;`
491
492			`when stopcc => -- stop clock counter`
493			`stopclockcount <= '1';`
494			`nextstate <= echo;`
495
496			`when ccstatus => -- get status of clock counter`
497			`in_buffer(7 downto 1) <= (others => '0');`
498			`in_buffer(0) <= clockcountstatus;`
499			`load <= '1';`
500			`nextstate <= busy8;`
501
502			`when getcc => -- get clockcounter value`
503			`in_buffer(31 downto 0) <= clockcounter;`
504			`load <= '1';`
505			`nextstate <= busy32;`
506
507
508			`-- READ MEMORY STATES --`
509			`when mem_read1 => -- complete operation from cpu`
510			`tomemory <= '1';`
511			`if mem_ready = '0' then`
512			`nextstate <= mem_read1;`
513			`else`
514			`nextstate <= mem_read2;`
515			`end if;`
516
517			`when mem_read2 => -- switch from cpu to debugger control`
518			`mem_switch <= '1';`
519			`nextstate <= mem_read3;`
520
521			`when mem_read3 => -- start operation`
522			`mem_switch <= '1';`
523			`mem_access_dbg <= "010";`
524
525			`if mem_ready = '1' then`
526			`nextstate <= mem_read3;`
527			`else`
528			`nextstate <= mem_read4;`
529			`end if;`
530
531			`when mem_read4 => -- finish operation`
532			`mem_switch <= '1';`
533			`mem_access_dbg <= "010";`
534
535			`load_mem_data <= '1';`
536
537			`if mem_ready = '1' then`
538			`nextstate <= mem_restore1;`
539			`else`
540			`nextstate <= mem_read4;`
541			`end if;`
542
543
544			`-- WRITE MEMORY STATES --`
545			`when mem_write1 => -- complete operation from cpu`
546			`tomemory <= '1';`
547
548			`if mem_ready = '0' then`
549			`nextstate <= mem_write1;`
550			`else`
551			`nextstate <= mem_write2;`
552			`end if;`
553
554			`when mem_write2 => -- switch from cpu to debugger control`
555			`mem_switch <= '1';`
556			`nextstate <= mem_write3;`
557
558
559			`when mem_write3 => -- start operation`
560			`mem_switch <= '1';`
561			`mem_access_dbg <= "100";`
562
563			`if mem_ready = '0' then`
564			`nextstate <= mem_write4;`
565			`else`
566			`nextstate <= mem_write3;`
567			`end if;`
568
569			`when mem_write4 => -- finish operation`
570			`mem_switch <= '1';`
571			`mem_access_dbg <= "100";`
572
573			`if mem_ready = '1' then`
574			`nextstate <= mem_restore1;`
575			`else`
576			`nextstate <= mem_write4;`
577			`end if;`
578
579
580			`-- RESTORE PREVIOUS MEMORY STATES --`
581			`when mem_restore1 => -- switch from debugger to cpu control`
582			`mem_switch <= '1';`
583			`nextstate <= mem_restore2;`
584
585			`when mem_restore2 =>`
586			`nextstate <= mem_restore3;`
587
588			`when mem_restore3 => -- wait for completition`
589			`if mem_ready = '0' then`
590			`nextstate <= mem_restore3;`
591			`else`
592			`nextstate <= mem_restore4;`
593			`end if;`
594
595			`when mem_restore4 => -- send back answer via rs232`
596			`todebug <= '1';`
597
598			`if data_rx = "00110010" then`
599			`nextstate <= busy32; -- read (send 32 bit data back)`
600			`else`
601			`nextstate <= echo; -- write (send ok back)`
602			`end if;`
603
604
605			`-- FETCH ADDRESS VALUE --`
606			`when fetch_address =>`
607			`inc <= '1';`
608			`ar_shift <= '1';`
609
610			`if counter = "11" then`
611			`nextstate <= to_normal;`
612			`else`
613			`nextstate <= echo;`
614			`end if;`
615
616			`-- FETCH DATA VALUE --`
617			`when fetch_data =>`
618			`inc <= '1';`
619			`dr_shift <= '1';`
620
621			`if counter = "11" then`
622			`nextstate <= to_normal;`
623			`else`
624			`nextstate <= echo;`
625			`end if;`
626
627			`-- SWITCH TO FETCH ADDRESS MODE --`
628			`when to_fetch_address =>`
629			`st_input <= "01";`
630			`st_set <= '1';`
631			`nextstate <= echo;`
632
633			`-- SWITCH TO FETCH DATA MODE --`
634			`when to_fetch_data =>`
635			`st_input <= "10";`
636			`st_set <= '1';`
637			`nextstate <= echo;`
638
639			`-- SWITCH TO NORMAL ADDRESS MODE --`
640			`when to_normal =>`
641			`st_input <= "00";`
642			`st_set <= '1';`
643			`nextstate <= echo;`
644
645			`-- SWITCH OT FREE RUNNING MODE --`
646			`when go =>`
647			`tofree <= '1';`
648			`nextstate <= echo;`
649
650			`-- END FREE RUNNING MODE --`
651			`when pause =>`
652			`todebug <= '1';`
653			`nextstate <= echo;`
654
655			`-- GENERATE ONE CLOCKTICK --`
656			`when clock =>`
657			`clocktick <= '1';`
658			`nextstate <= echo;`
659
660			`-- RESET CPU --`
661			`when reset1 =>`
662			`reset_out <= '1';`
663			`clocktick <= '1';`
664			`nextstate <= reset2;`
665
666			`when reset2 =>`
667			`reset_out <= '1';`
668			`nextstate <= echo;`
669
670			`-- SEND FLAGS --`
671			`when flags =>`
672			`in_buffer(7 downto 0) <= ir_ready & mem_ready & mem_access & halted & zero & carry;`
673			`load <= '1';`
674			`nextstate <= busy8;`
675
676			`-- SEND AKKUMULATOR --`
677			`when rega =>`
678			`in_buffer(31 downto 0) <= a;`
679			`load <= '1';`
680			`nextstate <= busy32;`
681
682			`-- SEND REGISTER X --`
683			`when regx =>`
684			`in_buffer(31 downto 0) <= x;`
685			`load <= '1';`
686			`nextstate <= busy32;`
687
688			`-- SEND REGISTER > --`
689			`when regy =>`
690			`in_buffer(31 downto 0) <= y;`
691			`load <= '1';`
692			`nextstate <= busy32;`
693
694			`-- SEND INSTRUCTION REGISTER --`
695			`when regir =>`
696			`in_buffer(31 downto 0) <= ir;`
697			`load <= '1';`
698			`nextstate <= busy32;`
699
700			`-- SEND INSTRUCTION COUNTER --`
701			`when regic =>`
702			`in_buffer(31 downto 0) <= ic;`
703			`load <= '1';`
704			`nextstate <= busy32;`
705
706			`-- SEND MEMORY ADDRESS --`
707			`when ma =>`
708			`in_buffer(31 downto 0) <= mem_addr;`
709			`load <= '1';`
710			`nextstate <= busy32;`
711
712			`-- SEND MEMORY DATA --`
713			`when md =>`
714			`in_buffer(31 downto 0) <= mem_data;`
715			`load <= '1';`
716			`nextstate <= busy32;`
717
718			`-- SEND RECEIVED COMMAND BACK --`
719			`when echo =>`
720			`in_buffer(7 downto 0) <= data_rx;`
721			`load <= '1';`
722			`nextstate <= busy8;`
723
724
725			`-- COMMON SENDING ROUTINES --`
726			`when busy8 =>`
727			`if tx_busy = '0' then`
728			`nextstate <= init8;`
729			`else`
730			`nextstate <= busy8;`
731			`end if;`
732
733			`when init8 =>`
734			`data_tx <= out_buffer(7 downto 0);`
735			`send_data <= '1';`
736
737			`if tx_busy = '1' then`
738			`nextstate <= sending8;`
739			`else`
740			`nextstate <= init8;`
741			`end if;`
742
743			`when sending8 =>`
744			`if tx_busy = '0' then`
745			`nextstate <= waiting;`
746			`else`
747			`nextstate <= sending8;`
748			`end if;`
749
750			`when busy32 =>`
751			`if tx_busy = '0' then`
752			`nextstate <= init32;`
753			`else`
754			`nextstate <= busy32;`
755			`end if;`
756
757			`when init32 =>`
758			`case counter is`
759			`when "00" =>`
760			`data_tx <= out_buffer(7 downto 0);`
761			`when "01" =>`
762			`data_tx <= out_buffer(15 downto 8);`
763			`when "10" =>`
764			`data_tx <= out_buffer(23 downto 16);`
765			`when "11" =>`
766			`data_tx <= out_buffer(31 downto 24);`
767			`when others =>`
768			`data_tx <= (others => '0');`
769			`end case;`
770
771			`send_data <= '1';`
772
773			`if tx_busy = '1' then`
774			`nextstate <= sending32;`
775			`else`
776			`nextstate <= init32;`
777			`end if;`
778
779			`when sending32 =>`
780			`if tx_busy = '0' then`
781			`nextstate <= inc32;`
782			`else`
783			`nextstate <= sending32;`
784			`end if;`
785
786			`when inc32 =>`
787			`inc <= '1';`
788
789			`if counter = "11" then`
790			`nextstate <= send_checksum;`
791			`else`
792			`nextstate <= busy32;`
793			`end if;`
794
795			`-- send checksum for 32 bit data`
796			`when send_checksum =>`
797			`data_tx <= checksum;`
798			`send_data <= '1';`
799
800			`if tx_busy = '1' then`
801			`nextstate <= sending8;`
802			`else`
803			`nextstate <= send_checksum;`
804			`end if;`
805
806			`end case;`
807			`end process;`
808			`end rtl;`