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[/] [hicovec/] [trunk/] [cpu/] [units/] [demultiplexer1x4.vhd] - Blame information for rev 12

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------------------------------------------------------------------
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-- PROJECT:      HiCoVec (highly configurable vector processor)
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--
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-- ENTITY:      demultiplexer1x4
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--
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-- PURPOSE:     demultiplexer, one input, four outputs
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--
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-- AUTHOR:      harald manske, haraldmanske@gmx.de
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--
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-- VERSION:     1.0
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-----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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entity demultiplexer1x4 is
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    port(   selector:       in std_logic_vector(1 downto 0);
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            data_in:        in std_logic;
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            data_out_00:    out std_logic;
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            data_out_01:    out std_logic;
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            data_out_10:    out std_logic;
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            data_out_11:    out std_logic
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         );
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end demultiplexer1x4;
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architecture rtl of demultiplexer1x4 is
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begin
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   data_out_00 <= data_in when selector = "00" else '0';
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   data_out_01 <= data_in when selector = "01" else '0';
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   data_out_10 <= data_in when selector = "10" else '0';
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   data_out_11 <= data_in when selector = "11" else '0';
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end rtl;
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