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[/] [hicovec/] [trunk/] [cpu/] [units/] [instructioncounter.vhd] - Blame information for rev 5

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------------------------------------------------------------------
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-- PROJECT:      HiCoVec (highly configurable vector processor)
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--
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-- ENTITY:      instructioncounter
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--
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-- PURPOSE:     instruction counter
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--              basically a 32 bit register with increment
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--
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-- AUTHOR:      harald manske, haraldmanske@gmx.de
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--
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-- VERSION:     1.0
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-----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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entity instructioncounter is
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    port(   clk:        in std_logic;
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            load:       in std_logic;
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            inc:        in std_logic;
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            reset:      in std_logic;
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            data_in:    in std_logic_vector(31 downto 0);
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            data_out:   out std_logic_vector(31 downto 0)
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         );
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end instructioncounter;
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architecture rtl of instructioncounter is
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    signal data_out_buffer:  unsigned(31 downto 0);
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begin
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    process
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    begin
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        wait until clk='1' and clk'event;
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        if reset = '1' then
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            data_out_buffer <= "00000000000000000000000000000000";
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        else
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            if load = '1' and inc = '0' then
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                data_out_buffer <= unsigned(data_in);
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            end if;
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            if load = '0' and inc = '1' then
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                data_out_buffer <= data_out_buffer + inc;
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            end if;
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            if (load = inc) then
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                data_out_buffer <= data_out_buffer;
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            end if;
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        end if;
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        end process;
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    data_out <= std_logic_vector(data_out_buffer);
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end rtl;
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