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[/] [hicovec/] [trunk/] [cpu/] [units/] [memoryinterface.vhd] - Blame information for rev 12

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------------------------------------------------------------------
-- PROJECT:      HiCoVec (highly configurable vector processor)
--
-- ENTITY:      memoryinterface
--
-- PURPOSE:     memory interface
--              for sram
--
-- AUTHOR:      harald manske, haraldmanske@gmx.de
--
-- VERSION:     1.0
-----------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
use work.cfg.all;
use work.datatypes.all;
 
-- WE, OE, SELECT
-- high-active, high-active, 0..scalar 1..vector
 
entity memoryinterface is
   port (
        clk:            in  std_logic;
        address:        in  std_logic_vector(31 downto 0) := (others => '0');
        access_type:    in  std_logic_vector(2 downto 0) := "000"; -- we, oe, cs
        data_in:        in  std_logic_vector(31 downto 0);
        vdata_in:       in  vectordata_type;
        data_out:       out std_logic_vector(31 downto 0);
        vdata_out:      out vectordata_type;
        ready:          out std_logic;
        we:             out std_logic;
        en:             out std_logic;
        addr:           out std_logic_vector(31 downto 0);
        di:             out std_logic_vector(31 downto 0);
        do:             in std_logic_vector(31 downto 0)
    );
end memoryinterface;
 
architecture rtl of memoryinterface is
 
    signal vload : std_logic;
    signal vdata_buffer : vectordata_type := (others => (others => '0'));
 
    signal inc: std_logic;
    signal res: std_logic;
    signal index: integer range 0 to k-1;
    signal counter : std_logic_vector(31 downto 0) := (others => '0');
 
    type statetype is (waiting, rw, vr1, vr2, vw1, vw2, vdone1, vdone2);
    signal state : statetype := waiting;
    signal nextstate : statetype := waiting;
 
begin
    -- derive index from counter
    index <= conv_integer(counter) when (counter < k) else 0;
 
    -- counter
    process
    begin
        wait until clk='1' and clk'event;
        counter <= counter;
 
        if res = '1' then
            counter <= (others => '0');
        else
            if inc = '1' then
                counter <= counter + '1';
            end if;
        end if;
    end process;
 
 
    -- vregister
    process
    begin
        wait until clk='1' and clk'event;
        if vload = '1' then
            vdata_buffer(index) <= do;
        else
            vdata_buffer(index) <= vdata_buffer(index);
        end if;
    end process;
 
    -- state register
    process
    begin
        wait until clk='1' and clk'event;
        state <= nextstate;
    end process;
 
    -- state transition
    process (clk, address, access_type, data_in, vdata_in, state, do, index, counter)
    begin
        ready <= '0';
        nextstate <= waiting;
 
        res <= '0';
        inc <= '0';
 
        vload <= '0';
 
        we <= '0';
        en <= '0';
        addr <= (others => '0');
        di <= (others => '0');
 
        case state is
            -- WAITING STATE
            when waiting =>
                ready <= '1';
 
                case access_type is
                    when "010" =>   -- scalar read
                        ready <= '0';
                        en <= '1';
                        addr <= address;
 
                        nextstate <= rw;
 
                    when "100" =>   -- scalar write
                        ready <= '0';
                        en <= '1';
                        addr <= address;
                        we <= '1';
                        di <= data_in;
 
                        nextstate <= rw;
 
                    when "011" =>   -- vector read
                        ready <= '0';
                        nextstate <= vr1;
 
                    when "101" =>   -- scalar write
                        ready <= '0';
                        nextstate <= vw1;
 
                    when others =>
                        nextstate <= waiting;
                end case;
 
            -- READ/WRITE DONE STATE
            when rw =>
                en <= '1';
                addr <= address;
                ready <= '1';
 
                if access_type = "000" then
                    nextstate <= waiting;
                else
                    nextstate <= rw;
                end if;
 
 
            -- VECTOR READ STATES
            when vr1 =>
                en <= '1';
                addr <= address + counter;
                nextstate <= vr2;
 
            when vr2 =>
                en <= '1';
                addr <= address + counter;
 
                inc <= '1';
                vload <= '1';
 
                if counter = k-1 then
                    nextstate <= vdone1;
                else
                    nextstate <= vr1;
                end if;
 
            -- VECTOR WRITE STATES
            when vw1 =>
                en <= '1';
                we <= '1';
                addr <= address + counter;
                di <= vdata_in(index);
 
                nextstate <= vw2;
 
            when vw2 =>
                en <= '1';
                addr <= address + counter;
                vload <= '1';
                inc <= '1';
 
                if counter = k-1 then
                    nextstate <= vdone1;
                else
                    nextstate <= vw1;
                end if;
 
 
            -- VECTOR DONE STATE
            when vdone1 =>
                res <= '1';
                nextstate <= vdone2;
 
            when vdone2 =>
                ready <= '1';
 
                if access_type = "000" then
                    nextstate <= waiting;
                else
                    nextstate <= vdone2;
                end if;
        end case;
    end process;
 
    -- connect outputs
    data_out <= do;
    vdata_out <= vdata_buffer;
end;
 

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Subversion Repositories hicovec

[/] [hicovec/] [trunk/] [cpu/] [units/] [memoryinterface.vhd] - Blame information for rev 12

Line No.	Rev	Author	Line
1	2	hmanske	`------------------------------------------------------------------`
2	4	hmanske	`-- PROJECT: HiCoVec (highly configurable vector processor)`
3	2	hmanske	`--`
4			`-- ENTITY: memoryinterface`
5			`--`
6			`-- PURPOSE: memory interface`
7			`-- for sram`
8			`--`
9			`-- AUTHOR: harald manske, haraldmanske@gmx.de`
10			`--`
11			`-- VERSION: 1.0`
12			`-----------------------------------------------------------------`
13
14			`library ieee;`
15			`use ieee.std_logic_1164.all;`
16			`use ieee.std_logic_arith.all;`
17			`use ieee.numeric_std.all;`
18			`use ieee.std_logic_unsigned.all;`
19
20			`use work.cfg.all;`
21			`use work.datatypes.all;`
22
23			`-- WE, OE, SELECT`
24			`-- high-active, high-active, 0..scalar 1..vector`
25
26			`entity memoryinterface is`
27			`port (`
28			`clk: in std_logic;`
29			`address: in std_logic_vector(31 downto 0) := (others => '0');`
30			`access_type: in std_logic_vector(2 downto 0) := "000"; -- we, oe, cs`
31			`data_in: in std_logic_vector(31 downto 0);`
32			`vdata_in: in vectordata_type;`
33			`data_out: out std_logic_vector(31 downto 0);`
34			`vdata_out: out vectordata_type;`
35			`ready: out std_logic;`
36			`we: out std_logic;`
37			`en: out std_logic;`
38			`addr: out std_logic_vector(31 downto 0);`
39			`di: out std_logic_vector(31 downto 0);`
40			`do: in std_logic_vector(31 downto 0)`
41			`);`
42			`end memoryinterface;`
43
44			`architecture rtl of memoryinterface is`
45
46			`signal vload : std_logic;`
47			`signal vdata_buffer : vectordata_type := (others => (others => '0'));`
48
49			`signal inc: std_logic;`
50			`signal res: std_logic;`
51			`signal index: integer range 0 to k-1;`
52			`signal counter : std_logic_vector(31 downto 0) := (others => '0');`
53
54			`type statetype is (waiting, rw, vr1, vr2, vw1, vw2, vdone1, vdone2);`
55			`signal state : statetype := waiting;`
56			`signal nextstate : statetype := waiting;`
57
58			`begin`
59			`-- derive index from counter`
60			`index <= conv_integer(counter) when (counter < k) else 0;`
61
62			`-- counter`
63			`process`
64			`begin`
65			`wait until clk='1' and clk'event;`
66			`counter <= counter;`
67
68			`if res = '1' then`
69			`counter <= (others => '0');`
70			`else`
71			`if inc = '1' then`
72			`counter <= counter + '1';`
73			`end if;`
74			`end if;`
75			`end process;`
76
77
78			`-- vregister`
79			`process`
80			`begin`
81			`wait until clk='1' and clk'event;`
82			`if vload = '1' then`
83			`vdata_buffer(index) <= do;`
84			`else`
85			`vdata_buffer(index) <= vdata_buffer(index);`
86			`end if;`
87			`end process;`
88
89			`-- state register`
90			`process`
91			`begin`
92			`wait until clk='1' and clk'event;`
93			`state <= nextstate;`
94			`end process;`
95
96			`-- state transition`
97			`process (clk, address, access_type, data_in, vdata_in, state, do, index, counter)`
98			`begin`
99			`ready <= '0';`
100			`nextstate <= waiting;`
101
102			`res <= '0';`
103			`inc <= '0';`
104
105			`vload <= '0';`
106
107			`we <= '0';`
108			`en <= '0';`
109			`addr <= (others => '0');`
110			`di <= (others => '0');`
111
112			`case state is`
113			`-- WAITING STATE`
114			`when waiting =>`
115			`ready <= '1';`
116
117			`case access_type is`
118			`when "010" => -- scalar read`
119			`ready <= '0';`
120			`en <= '1';`
121			`addr <= address;`
122
123			`nextstate <= rw;`
124
125			`when "100" => -- scalar write`
126			`ready <= '0';`
127			`en <= '1';`
128			`addr <= address;`
129			`we <= '1';`
130			`di <= data_in;`
131
132			`nextstate <= rw;`
133
134			`when "011" => -- vector read`
135			`ready <= '0';`
136			`nextstate <= vr1;`
137
138			`when "101" => -- scalar write`
139			`ready <= '0';`
140			`nextstate <= vw1;`
141
142			`when others =>`
143			`nextstate <= waiting;`
144			`end case;`
145
146			`-- READ/WRITE DONE STATE`
147			`when rw =>`
148			`en <= '1';`
149			`addr <= address;`
150			`ready <= '1';`
151
152			`if access_type = "000" then`
153			`nextstate <= waiting;`
154			`else`
155			`nextstate <= rw;`
156			`end if;`
157
158
159			`-- VECTOR READ STATES`
160			`when vr1 =>`
161			`en <= '1';`
162			`addr <= address + counter;`
163			`nextstate <= vr2;`
164
165			`when vr2 =>`
166			`en <= '1';`
167			`addr <= address + counter;`
168
169			`inc <= '1';`
170			`vload <= '1';`
171
172			`if counter = k-1 then`
173			`nextstate <= vdone1;`
174			`else`
175			`nextstate <= vr1;`
176			`end if;`
177
178			`-- VECTOR WRITE STATES`
179			`when vw1 =>`
180			`en <= '1';`
181			`we <= '1';`
182			`addr <= address + counter;`
183			`di <= vdata_in(index);`
184
185			`nextstate <= vw2;`
186
187			`when vw2 =>`
188			`en <= '1';`
189			`addr <= address + counter;`
190			`vload <= '1';`
191			`inc <= '1';`
192
193			`if counter = k-1 then`
194			`nextstate <= vdone1;`
195			`else`
196			`nextstate <= vw1;`
197			`end if;`
198
199
200			`-- VECTOR DONE STATE`
201			`when vdone1 =>`
202			`res <= '1';`
203			`nextstate <= vdone2;`
204
205			`when vdone2 =>`
206			`ready <= '1';`
207
208			`if access_type = "000" then`
209			`nextstate <= waiting;`
210			`else`
211			`nextstate <= vdone2;`
212			`end if;`
213			`end case;`
214			`end process;`
215
216			`-- connect outputs`
217			`data_out <= do;`
218			`vdata_out <= vdata_buffer;`
219			`end;`
220