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[/] [hicovec/] [trunk/] [cpu/] [units/] [multiplexer2.vhd] - Blame information for rev 12

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------------------------------------------------------------------
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-- PROJECT:      HiCoVec (highly configurable vector processor)
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--
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-- ENTITY:      multiplexer2
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--
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-- PURPOSE:     multiplexer, two inputs
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--              one output
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--
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-- AUTHOR:      harald manske, haraldmanske@gmx.de
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--
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-- VERSION:     1.0
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-----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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entity multiplexer2 is
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    generic (
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        w : positive -- word width
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    );
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    port (
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        selector:   in std_logic;
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        data_in_0:  in std_logic_vector(w-1 downto 0);
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        data_in_1:  in std_logic_vector(w-1 downto 0);
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        data_out:   out std_logic_vector(w-1 downto 0)
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    );
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end multiplexer2;
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architecture rtl of multiplexer2 is
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begin
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   data_out <=  data_in_0 when selector = '0' else
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                data_in_1;
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end rtl;
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