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----------------------------------------------------------------------------------
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-- Company: Fachhochschule Augsburg - Fakultät für Informatik
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-- Engineer: Schäferling Michael
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--
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-- Create Date: 23:34:55 02/27/2007
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-- Design Name:
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-- Module Name: rs232 - Behavioral
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-- Project Name:
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-- Target Devices: Xilinx
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-- Tool versions:
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-- Description: This module provides RS232 communication
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity rs232 is
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generic(DATABITS: integer:= 8;
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STARTBITS: integer:= 1;
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STOPBITS: integer:= 1
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);
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port( -- HW signalling
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CLK_50MHZ : in std_logic;
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RS232_RXD: in std_logic;
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RS232_TXD: out std_logic := '1';
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-- internal DataCom
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DATA_TX : in std_logic_vector(DATABITS-1 downto 0);
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TX_SEND_DATA : in std_logic;
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TX_BUSY : out std_logic := '0';
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DATA_RX : out std_logic_vector(DATABITS-1 downto 0) := (others => '0');
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RX_DATA_RCVD : out std_logic := '0';
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RX_BUSY : out std_logic := '0'
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);
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end rs232;
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architecture Behavioral of rs232 is
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type SER_STATES is (IDLE, SYN, B0, B1, B2, B3, B4, B5, B6, B7, VALID);
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signal SER_STATE: SER_STATES := IDLE;
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signal CLK_38400: std_logic := '0';
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signal SIG_RST_TSER2: std_logic := '0';
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signal SIG_TSER2: std_logic := '0';
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signal SIG_RST_TSER: std_logic := '0';
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signal SIG_TSER: std_logic := '0';
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begin
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-- Generate Signal for Serial Clock at 38400
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P_GEN_CLK38400: process (CLK_50MHZ)
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-- 1302 == 10100010110
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constant CLK38400_MAX: std_logic_vector(10 downto 0) := "10100010110";
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variable CLK38400_CUR: std_logic_vector(10 downto 0) := "00000000000";
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begin
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if CLK_50MHZ'event AND CLK_50MHZ='1' then
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if CLK38400_CUR = CLK38400_MAX then
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CLK38400_CUR := (others => '0');
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CLK_38400 <= '1';
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else
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CLK38400_CUR := CLK38400_CUR + "00000000001";
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CLK_38400 <= '0';
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end if;
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end if;
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end process P_GEN_CLK38400;
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-- Generate Reset-driven Signal after Tser/2
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P_GEN_SIG_TSER2: process (CLK_50MHZ)
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-- 651 == 1010001011
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constant TSER2_MAX: std_logic_vector(9 downto 0) := "1010001011";
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variable TSER2_CUR: std_logic_vector(9 downto 0) := "0000000000";
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begin
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if CLK_50MHZ'event AND CLK_50MHZ='1' then
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if SIG_RST_TSER2 = '1' then
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SIG_TSER2 <= '0';
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TSER2_CUR := (others => '0');
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elsif TSER2_CUR = TSER2_MAX then
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SIG_TSER2 <= '1';
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TSER2_CUR := (others => '0');
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else
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SIG_TSER2 <= '0';
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TSER2_CUR := TSER2_CUR + "0000000001";
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end if;
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end if;
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end process P_GEN_SIG_TSER2;
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-- Generate Reset-driven Signal after Tser
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P_GEN_SIG_TSER: process (CLK_50MHZ)
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constant TSER_MAX: std_logic_vector(10 downto 0) := "10100010110";
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variable TSER_CUR: std_logic_vector(10 downto 0) := "00000000000";
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begin
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if CLK_50MHZ'event AND CLK_50MHZ='1' then
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if SIG_RST_TSER = '1' then
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SIG_TSER <= '0';
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TSER_CUR := (others => '0');
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elsif TSER_CUR = TSER_MAX then
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SIG_TSER <= '1';
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TSER_CUR := (others => '0');
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else
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SIG_TSER <= '0';
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TSER_CUR := TSER_CUR + "00000000001";
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end if;
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end if;
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end process P_GEN_SIG_TSER;
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-- RX / TX Process
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P_RX_TX: process (CLK_50MHZ)
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constant TOKENSIZE: integer:= STARTBITS + DATABITS + STOPBITS;
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-- variables for RX
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variable BYTE_RX: std_logic_vector(7 downto 0);
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-- for testing
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variable signcount: std_logic_vector(3 downto 0) := "0000";
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-- variables for TX
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variable SEND_TOKEN: std_logic := '0';
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variable TOKEN_OUT: std_logic_vector(TOKENSIZE-1 downto 0);
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variable COUNT: std_logic_vector(3 downto 0) := "0000";
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begin
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if CLK_50MHZ'event AND CLK_50MHZ='1' then
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-- RX
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RX_BUSY <= '1';
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case SER_STATE is
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when IDLE => if RS232_RXD = '0' then
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SIG_RST_TSER2 <= '1';
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SER_STATE <= SYN;
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RX_DATA_RCVD <= '0';
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else
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RX_BUSY <= '0';
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SIG_RST_TSER2 <= '0';
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SER_STATE <= IDLE;
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RX_DATA_RCVD <= '0';
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end if;
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when SYN => if SIG_TSER2 = '1' then
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SIG_RST_TSER2 <= '0';
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SIG_RST_TSER <= '1';
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SER_STATE <= B0;
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else
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SIG_RST_TSER2 <= '0';
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SIG_RST_TSER <= '0';
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SER_STATE <= SYN;
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end if;
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when B0 => if SIG_TSER = '1' then
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SIG_RST_TSER <= '0';
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SER_STATE <= B1;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else
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SIG_RST_TSER <= '0';
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SER_STATE <= B0;
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end if;
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when B1 => if SIG_TSER = '1' then
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SER_STATE <= B2;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else SER_STATE <= B1;
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end if;
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when B2 => if SIG_TSER = '1' then
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SER_STATE <= B3;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else SER_STATE <= B2;
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end if;
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when B3 => if SIG_TSER = '1' then
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SER_STATE <= B4;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else SER_STATE <= B3;
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end if;
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when B4 => if SIG_TSER = '1' then
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SER_STATE <= B5;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else SER_STATE <= B4;
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end if;
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when B5 => if SIG_TSER = '1' then
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SER_STATE <= B6;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else SER_STATE <= B5;
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end if;
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when B6 => if SIG_TSER = '1' then
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SER_STATE <= B7;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else SER_STATE <= B6;
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end if;
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when B7 => if SIG_TSER = '1' then
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SER_STATE <= VALID;
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BYTE_RX := RS232_RXD & BYTE_RX(7 downto 1);
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else SER_STATE <= B7;
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end if;
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when VALID => if SIG_TSER = '1' then
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if RS232_RXD = '1' then
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DATA_RX <= BYTE_RX;
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RX_DATA_RCVD <= '1';
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else
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DATA_RX <= (others => '0');
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RX_DATA_RCVD <= '0';
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end if;
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SER_STATE <= IDLE;
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else
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SER_STATE <= VALID;
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end if;
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end case;
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-- TX
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TX_BUSY <= '0';
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if TX_SEND_DATA = '1' AND SEND_TOKEN = '0' then
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TOKEN_OUT := '1' & DATA_TX & '0';
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SEND_TOKEN := '1';
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end if;
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if SEND_TOKEN = '1' then
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TX_BUSY <= '1';
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if CLK_38400 = '1' then
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if COUNT < TOKENSIZE then
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--TX_BUSY <= '1';
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COUNT := COUNT + "0001";
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-- send from right to left (LSB first)
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RS232_TXD <= TOKEN_OUT(0);
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TOKEN_OUT(TOKENSIZE-1 downto 0) := TOKEN_OUT(0) & TOKEN_OUT(TOKENSIZE-1 downto 1);
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else
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COUNT := "0000";
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SEND_TOKEN := '0';
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--TX_BUSY <= '0';
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end if;
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end if;
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--else
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--TX_BUSY <= '0';
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end if;
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end if;
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end process P_RX_TX;
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end Behavioral;
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