URL https://opencores.org/ocsvn/hicovec/hicovec/trunk

Subversion Repositories hicovec

[/] [hicovec/] [trunk/] [cpu/] [units/] [vector_controlunit.vhd] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log


------------------------------------------------------------------
-- PROJECT:      HiCoVec (highly configurable vector processor)
--
-- ENTITY:      vector_controlunit
--
-- PURPOSE:     controlunit for vector unit
--
-- AUTHOR:      harald manske, haraldmanske@gmx.de
--
-- VERSION:     1.0
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
 
use work.cfg.all;
 
entity vector_controlunit is
    port(
        -- clock
        clk:            in std_logic;                       -- clock signal
 
        -- instruction in
        ir:             in std_logic_vector(31 downto 0);   -- instruction
 
        -- control signals out
        load_r:         out std_logic;
        cc9:            out std_logic_vector(1 downto 0);
        c10:            out std_logic;
        c11:            out std_logic;
        c12:            out std_logic;
        cc13:           out std_logic_vector(1 downto 0);
        valu_go:        out std_logic;
        shuffle_go:     out std_logic;
 
        -- control signals in
        out_valid:      in  std_logic;
        shuffle_valid:  in  std_logic;
 
        -- communication with scalar unit
        ir_ready:       in std_logic;                       -- next instruction has been loaded into ir
        s_ready:        in std_logic;                       -- data from scalar unit or mi is ready
        s_fetched:      in std_logic;                       -- signal for vector unit to continue
 
        v_ready:        out std_logic;                      -- data for scalar unit or mi is ready
        v_fetched:      out std_logic;                      -- signal for scalar unit to continue
        v_done:         out std_logic                       -- vector unit completed command
    );
end vector_controlunit;
 
architecture rtl of vector_controlunit is
    type statetype is (wfi, decode_wait, vmovrv, vmovrrn, vmovrnv, valu1, valu2, valu3, vld, vtos,
                       movrts, mova, shuffle1, shuffle2, shuffle3, vmol, vmor);
 
    signal state : statetype := wfi;
    signal nextstate : statetype := wfi;
 
begin
 
    -- state register
    process
    begin
        wait until clk='1' and clk'event;
        state <= nextstate;
 
    end process;
 
    -- state transitions
    process (state, ir, ir_ready, s_ready, s_fetched, out_valid, shuffle_valid)
    begin
        -- avoid latches
        load_r      <= '0';
        cc9         <= "00";
        c10         <= '0';
        c11         <= '0';
        c12         <= '0';
        cc13        <= "00";
        v_ready     <= '0';
        v_fetched   <= '0';
        v_done      <= '0';
        valu_go     <= '0';
        shuffle_go  <= '0';
 
        nextstate   <= wfi;
 
        case state is
 
            -- WAIT FOR INSTRUCTION STATE --
            when wfi =>
                 if ir_ready = '1' then
                    nextstate <= decode_wait;
                else
                    v_done <= '1';
                    nextstate <= wfi;
                end if;
 
            -- DECODE AND WAIT STATE --
            when decode_wait =>
                case ir(19 downto 18) is
                    when "00" =>
                        if ir(17) = '0' then                        -- vnop
                            nextstate <= wfi;
                        else
                            case ir(15 downto 12) is
                                when "0001" =>                      -- vmov r,v
                                    nextstate <= vmovrv;
 
                                when "0010" =>                      -- vmov r, R<n>
                                    nextstate <= vmovrrn;
 
                                when "0011" =>                      -- vmov R<n>, v
                                    nextstate <= vmovrnv;
 
                                when "1000" =>                      -- vmol r,v
                                    nextstate <= vmol;
 
                                when "1100" =>                      -- vmor r,v
                                    nextstate <= vmor;
 
                                when others =>                      -- error => ignore command
                                    nextstate <= wfi;
                            end case;
                         end if;
 
                    when "01" =>                                -- valu
                        nextstate <= valu1;
 
                    when "10" =>                                -- vld/vst/move
                        case ir(15 downto 12) is
                            when "0010" =>                      -- vld
                                if s_ready = '1' then
                                    nextstate <= vld;
                                else
                                    nextstate <= decode_wait;
                                end if;
 
                            when "0011" | "0101" =>             -- vst, mov d, v(t)
                                nextstate <= vtos;
 
                            when "0100" =>                      -- mov r(t), s
                                if s_ready = '1' then
                                    nextstate <= movrts;
                                else
                                    nextstate <= decode_wait;
                                end if;
 
                            when "0110" =>                      -- mova
                                if s_ready = '1' then
                                    nextstate <= mova;
                                else
                                    nextstate <= decode_wait;
                                end if;
 
                            when others =>                      -- error => ignore command
                                nextstate <= wfi;
                        end case;
 
                    when "11" =>                                -- shuffle
                        if use_shuffle then
                            nextstate <= shuffle1;
                        else
                            nextstate <= wfi;
                        end if;
                    when others =>                              -- error
                        nextstate <= wfi;
                end case;
 
            -- VMOL R,V STATE --
            when vmol =>
                cc13 <= "10";
                cc9 <= "11";
                load_r <= '1';
                nextstate <= wfi;
 
            -- VMOR R,V STATE --
            when vmor =>
                cc13 <= "11";
                cc9 <= "11";
                load_r <= '1';
                nextstate <= wfi;
 
            -- VMOV R,V STATE --
            when vmovrv =>
                cc13 <= "01";
                cc9 <= "11";
                load_r <= '1';
                nextstate <= wfi;
 
            -- VMOV R,R<N> STATE --
            when vmovrrn =>
                cc13 <= "01";
                cc9 <= "11";
                c11 <= '1';
                load_r <= '1';
                nextstate <= wfi;
 
            -- VMOV R<N>,V STATE --
            when vmovrnv =>
                cc13 <= "01";
                cc9 <= "11";
                c10 <= '1';
                load_r <= '1';
                nextstate <= wfi;
 
            -- VALU COMMAND STATE --
            when valu1 =>
                valu_go <= '1';
                nextstate <= valu2;
 
            when valu2 =>
                if out_valid = '0' then
                    nextstate <= valu2;
                else
                    nextstate <= valu3;
                end if;
 
            when valu3 =>
                load_r <= '1';
                nextstate <= wfi;
 
            -- VLD STATE --
            when vld =>
                cc9 <= "10";
                load_r <= '1';
                v_fetched <= '1';
                nextstate <= wfi;
 
            -- VECTOR TO SCALAR STATE --
            when vtos =>
                v_ready <= '1';
 
                if s_fetched = '1' then
                    nextstate <= wfi;
                else
                    nextstate <= vtos;
                end if;
 
            -- MOV R(T),S STATE --
            when movrts =>
                cc9 <= "01";
                c12 <= '1';
                load_r <= '1';
                v_fetched <= '1';
                nextstate <= wfi;
 
            -- MOVA STATE --
            when mova =>
                cc9 <= "01";
                load_r <= '1';
                v_fetched <= '1';
                nextstate <= wfi;
 
            -- SHUFFLE STATES
            when shuffle1 =>
                shuffle_go <= '1';
                nextstate <= shuffle2;
 
            when shuffle2 =>
                if shuffle_valid = '0' then
                    nextstate <= shuffle2;
                else
                    nextstate <= shuffle3;
                end if;
 
            when shuffle3 =>
                cc9 <= "11";
                load_r <= '1';
                nextstate <= wfi;
 
        end case;
        end process;
end rtl;
 

Browse

Tools

Subversion Repositories hicovec

[/] [hicovec/] [trunk/] [cpu/] [units/] [vector_controlunit.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	hmanske	`------------------------------------------------------------------`
2	4	hmanske	`-- PROJECT: HiCoVec (highly configurable vector processor)`
3	2	hmanske	`--`
4			`-- ENTITY: vector_controlunit`
5			`--`
6			`-- PURPOSE: controlunit for vector unit`
7			`--`
8			`-- AUTHOR: harald manske, haraldmanske@gmx.de`
9			`--`
10			`-- VERSION: 1.0`
11			`-----------------------------------------------------------------`
12			`library ieee;`
13			`use ieee.std_logic_1164.all;`
14			`use ieee.std_logic_arith.all;`
15			`use ieee.numeric_std.all;`
16
17			`use work.cfg.all;`
18
19			`entity vector_controlunit is`
20			`port(`
21			`-- clock`
22			`clk: in std_logic; -- clock signal`
23
24			`-- instruction in`
25			`ir: in std_logic_vector(31 downto 0); -- instruction`
26
27			`-- control signals out`
28			`load_r: out std_logic;`
29			`cc9: out std_logic_vector(1 downto 0);`
30			`c10: out std_logic;`
31			`c11: out std_logic;`
32			`c12: out std_logic;`
33			`cc13: out std_logic_vector(1 downto 0);`
34			`valu_go: out std_logic;`
35			`shuffle_go: out std_logic;`
36
37			`-- control signals in`
38			`out_valid: in std_logic;`
39			`shuffle_valid: in std_logic;`
40
41			`-- communication with scalar unit`
42			`ir_ready: in std_logic; -- next instruction has been loaded into ir`
43			`s_ready: in std_logic; -- data from scalar unit or mi is ready`
44			`s_fetched: in std_logic; -- signal for vector unit to continue`
45
46			`v_ready: out std_logic; -- data for scalar unit or mi is ready`
47			`v_fetched: out std_logic; -- signal for scalar unit to continue`
48			`v_done: out std_logic -- vector unit completed command`
49			`);`
50			`end vector_controlunit;`
51
52			`architecture rtl of vector_controlunit is`
53			`type statetype is (wfi, decode_wait, vmovrv, vmovrrn, vmovrnv, valu1, valu2, valu3, vld, vtos,`
54			`movrts, mova, shuffle1, shuffle2, shuffle3, vmol, vmor);`
55
56			`signal state : statetype := wfi;`
57			`signal nextstate : statetype := wfi;`
58
59			`begin`
60
61			`-- state register`
62			`process`
63			`begin`
64			`wait until clk='1' and clk'event;`
65			`state <= nextstate;`
66
67			`end process;`
68
69			`-- state transitions`
70			`process (state, ir, ir_ready, s_ready, s_fetched, out_valid, shuffle_valid)`
71			`begin`
72			`-- avoid latches`
73			`load_r <= '0';`
74			`cc9 <= "00";`
75			`c10 <= '0';`
76			`c11 <= '0';`
77			`c12 <= '0';`
78			`cc13 <= "00";`
79			`v_ready <= '0';`
80			`v_fetched <= '0';`
81			`v_done <= '0';`
82			`valu_go <= '0';`
83			`shuffle_go <= '0';`
84
85			`nextstate <= wfi;`
86
87			`case state is`
88
89			`-- WAIT FOR INSTRUCTION STATE --`
90			`when wfi =>`
91			`if ir_ready = '1' then`
92			`nextstate <= decode_wait;`
93			`else`
94			`v_done <= '1';`
95			`nextstate <= wfi;`
96			`end if;`
97
98			`-- DECODE AND WAIT STATE --`
99			`when decode_wait =>`
100			`case ir(19 downto 18) is`
101			`when "00" =>`
102			`if ir(17) = '0' then -- vnop`
103			`nextstate <= wfi;`
104			`else`
105			`case ir(15 downto 12) is`
106			`when "0001" => -- vmov r,v`
107			`nextstate <= vmovrv;`
108
109			`when "0010" => -- vmov r, R<n>`
110			`nextstate <= vmovrrn;`
111
112			`when "0011" => -- vmov R<n>, v`
113			`nextstate <= vmovrnv;`
114
115			`when "1000" => -- vmol r,v`
116			`nextstate <= vmol;`
117
118			`when "1100" => -- vmor r,v`
119			`nextstate <= vmor;`
120
121			`when others => -- error => ignore command`
122			`nextstate <= wfi;`
123			`end case;`
124			`end if;`
125
126			`when "01" => -- valu`
127			`nextstate <= valu1;`
128
129			`when "10" => -- vld/vst/move`
130			`case ir(15 downto 12) is`
131			`when "0010" => -- vld`
132			`if s_ready = '1' then`
133			`nextstate <= vld;`
134			`else`
135			`nextstate <= decode_wait;`
136			`end if;`
137
138			`when "0011" \| "0101" => -- vst, mov d, v(t)`
139			`nextstate <= vtos;`
140
141			`when "0100" => -- mov r(t), s`
142			`if s_ready = '1' then`
143			`nextstate <= movrts;`
144			`else`
145			`nextstate <= decode_wait;`
146			`end if;`
147
148			`when "0110" => -- mova`
149			`if s_ready = '1' then`
150			`nextstate <= mova;`
151			`else`
152			`nextstate <= decode_wait;`
153			`end if;`
154
155			`when others => -- error => ignore command`
156			`nextstate <= wfi;`
157			`end case;`
158
159			`when "11" => -- shuffle`
160			`if use_shuffle then`
161			`nextstate <= shuffle1;`
162			`else`
163			`nextstate <= wfi;`
164			`end if;`
165			`when others => -- error`
166			`nextstate <= wfi;`
167			`end case;`
168
169			`-- VMOL R,V STATE --`
170			`when vmol =>`
171			`cc13 <= "10";`
172			`cc9 <= "11";`
173			`load_r <= '1';`
174			`nextstate <= wfi;`
175
176			`-- VMOR R,V STATE --`
177			`when vmor =>`
178			`cc13 <= "11";`
179			`cc9 <= "11";`
180			`load_r <= '1';`
181			`nextstate <= wfi;`
182
183			`-- VMOV R,V STATE --`
184			`when vmovrv =>`
185			`cc13 <= "01";`
186			`cc9 <= "11";`
187			`load_r <= '1';`
188			`nextstate <= wfi;`
189
190			`-- VMOV R,R<N> STATE --`
191			`when vmovrrn =>`
192			`cc13 <= "01";`
193			`cc9 <= "11";`
194			`c11 <= '1';`
195			`load_r <= '1';`
196			`nextstate <= wfi;`
197
198			`-- VMOV R<N>,V STATE --`
199			`when vmovrnv =>`
200			`cc13 <= "01";`
201			`cc9 <= "11";`
202			`c10 <= '1';`
203			`load_r <= '1';`
204			`nextstate <= wfi;`
205
206			`-- VALU COMMAND STATE --`
207			`when valu1 =>`
208			`valu_go <= '1';`
209			`nextstate <= valu2;`
210
211			`when valu2 =>`
212			`if out_valid = '0' then`
213			`nextstate <= valu2;`
214			`else`
215			`nextstate <= valu3;`
216			`end if;`
217
218			`when valu3 =>`
219			`load_r <= '1';`
220			`nextstate <= wfi;`
221
222			`-- VLD STATE --`
223			`when vld =>`
224			`cc9 <= "10";`
225			`load_r <= '1';`
226			`v_fetched <= '1';`
227			`nextstate <= wfi;`
228
229			`-- VECTOR TO SCALAR STATE --`
230			`when vtos =>`
231			`v_ready <= '1';`
232
233			`if s_fetched = '1' then`
234			`nextstate <= wfi;`
235			`else`
236			`nextstate <= vtos;`
237			`end if;`
238
239			`-- MOV R(T),S STATE --`
240			`when movrts =>`
241			`cc9 <= "01";`
242			`c12 <= '1';`
243			`load_r <= '1';`
244			`v_fetched <= '1';`
245			`nextstate <= wfi;`
246
247			`-- MOVA STATE --`
248			`when mova =>`
249			`cc9 <= "01";`
250			`load_r <= '1';`
251			`v_fetched <= '1';`
252			`nextstate <= wfi;`
253
254			`-- SHUFFLE STATES`
255			`when shuffle1 =>`
256			`shuffle_go <= '1';`
257			`nextstate <= shuffle2;`
258
259			`when shuffle2 =>`
260			`if shuffle_valid = '0' then`
261			`nextstate <= shuffle2;`
262			`else`
263			`nextstate <= shuffle3;`
264			`end if;`
265
266			`when shuffle3 =>`
267			`cc9 <= "11";`
268			`load_r <= '1';`
269			`nextstate <= wfi;`
270
271			`end case;`
272			`end process;`
273			`end rtl;`
274