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[/] [hight/] [trunk/] [rtl/] [HIGHT_CORE_TOP.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Top module for HIGHT Crypto Core                            ////
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////                                                              ////
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////  This file is part of the HIGHT Crypto Core project          ////
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////  http://github.com/OpenSoCPlus/hight_crypto_core             ////
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////  http://www.opencores.org/project,hight                      ////
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////                                                              ////
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////  Description                                                 ////
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////  __description__                                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - JoonSoo Ha, json.ha@gmail.com                         ////
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////      - Younjoo Kim, younjookim.kr@gmail.com                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG    ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module HIGHT_CORE_TOP(
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        rstn         ,
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        clk          ,
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        i_mk_rdy     ,
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        i_mk         ,
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        i_post_rdy   ,
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        i_op         ,
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        i_text_val   ,
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        i_text_in    ,
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        o_text_done  ,
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        o_text_out   ,
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        o_rdy
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);
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//=====================================
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//
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//          PARAMETERS 
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//
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//=====================================
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//=====================================
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//
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//          I/O PORTS 
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//
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//=====================================
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input        rstn         ;
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input        clk          ;
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input        i_mk_rdy     ;
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input[127:0] i_mk         ;
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input        i_post_rdy   ;
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input        i_op         ;
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input        i_text_val   ;
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input[63:0]  i_text_in    ;
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output       o_text_done  ;
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output[63:0] o_text_out   ;
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output       o_rdy        ;
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//=====================================
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//
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//          REGISTERS
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//
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//=====================================
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//=====================================
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//
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//          WIRES
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//
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//=====================================
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wire[31:0]  w_rnd_key     ;
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wire[2:0]   w_xf_sel      ;
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wire        w_rf_final    ;
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wire        w_key_sel     ;
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wire[4:0]   w_rnd_idx     ;
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wire        w_wf_post_pre ;
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//=====================================
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//
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//          MAIN
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//
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//=====================================
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// CYPTO_PATH instance 
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CRYPTO_PATH u_CRYPTO_PATH(
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        .rstn           ( rstn          ) ,
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        .clk            ( clk           ) ,
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        .i_op           ( i_op          ) ,
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        .i_wrsk         ( w_rnd_key     ) ,
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        .i_text_in      ( i_text_in     ) ,
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        .i_xf_sel       ( w_xf_sel      ) ,
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        .i_rf_final     ( w_rf_final    ) ,
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        .o_text_out     ( o_text_out    )
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);
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// KEY_SCHED instance
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KEY_SCHED u_KEY_SCHED(
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        .rstn           ( rstn          ) ,
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        .clk            ( clk           ) ,
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        .i_mk           ( i_mk          ) ,
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        .i_op           ( i_op          ) ,
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        .i_key_sel      ( w_key_sel     ) ,
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        .i_rnd_idx      ( w_rnd_idx     ) ,
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        .i_wf_post_pre  ( w_wf_post_pre ) ,
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        .o_rnd_key      ( w_rnd_key     )
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);
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// CONTROL instance
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CONTROL u_CONTROL(
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        .rstn           ( rstn          ) ,
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        .clk            ( clk           ) ,
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        .i_mk_rdy       ( i_mk_rdy      ) ,
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        .i_post_rdy     ( i_post_rdy    ) ,
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        .i_text_val     ( i_text_val    ) ,
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        .o_rdy          ( o_rdy         ) ,
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        .o_text_done    ( o_text_done   ) ,
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        .o_xf_sel       ( w_xf_sel      ) ,
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        .o_rf_final     ( w_rf_final    ) ,
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        .o_key_sel      ( w_key_sel     ) ,
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        .o_rnd_idx      ( w_rnd_idx     ) ,
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        .o_wf_post_pre  ( w_wf_post_pre )
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);
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endmodule
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