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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Round function of main datapath for HIGHT Crypto Core ////
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//// ////
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//// This file is part of the HIGHT Crypto Core project ////
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//// http://github.com/OpenSoCPlus/hight_crypto_core ////
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//// http://www.opencores.org/project,hight ////
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//// ////
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//// Description ////
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//// __description__ ////
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//// ////
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//// Author(s): ////
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//// - JoonSoo Ha, json.ha@gmail.com ////
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//// - Younjoo Kim, younjookim.kr@gmail.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module RF(
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i_op ,
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i_rsk ,
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i_rf_in ,
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i_rf_final ,
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o_rf_out
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);
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//=====================================
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//
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// PARAMETERS
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//
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//=====================================
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//=====================================
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//
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// I/O PORTS
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//
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//=====================================
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input i_op ;
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input[31:0] i_rsk ;
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input[63:0] i_rf_in ;
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input i_rf_final ;
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output[63:0] o_rf_out ;
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//=====================================
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//
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// REGISTERS
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//
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//=====================================
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//=====================================
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//
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// WIRES
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//
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//=====================================
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// w_rf_out
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wire[63:0] w_rf_out ;
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// w_rf_out (7 ~ 0)
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wire[7:0] w_rf_out7 ;
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wire[7:0] w_rf_out6 ;
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wire[7:0] w_rf_out5 ;
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wire[7:0] w_rf_out4 ;
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wire[7:0] w_rf_out3 ;
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wire[7:0] w_rf_out2 ;
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wire[7:0] w_rf_out1 ;
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wire[7:0] w_rf_out0 ;
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// w_f_function
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wire[7:0] w_f0_6 ;
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wire[7:0] w_f1_4 ;
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wire[7:0] w_f0_2 ;
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wire[7:0] w_f1_0 ;
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// w_rf_median_value
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wire[7:0] w_rf_mv[0:3];
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//=====================================
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//
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// MAIN
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//
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//=====================================
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assign w_f0_6 = {i_rf_in[54:48],i_rf_in[55]} ^
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{i_rf_in[53:48],i_rf_in[55:54]} ^
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{i_rf_in[48] ,i_rf_in[55:49]};
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assign w_f1_4 = {i_rf_in[36:32],i_rf_in[39:37]} ^
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{i_rf_in[35:32],i_rf_in[39:36]} ^
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{i_rf_in[33:32],i_rf_in[39:34]};
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assign w_f0_2 = {i_rf_in[22:16],i_rf_in[23]} ^
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{i_rf_in[21:16],i_rf_in[23:22]} ^
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{i_rf_in[16] ,i_rf_in[23:17]};
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assign w_f1_0 = {i_rf_in[4:0] ,i_rf_in[7:5]} ^
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{i_rf_in[3:0] ,i_rf_in[7:4]} ^
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{i_rf_in[1:0] ,i_rf_in[7:2]};
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assign w_rf_mv[3] = (i_op == 0) ? i_rf_in[63:56] ^ (w_f0_6 + i_rsk[31:24]):
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i_rf_in[63:56] ^ (w_f0_6 + i_rsk[7:0]);
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assign w_rf_mv[2] = (i_op == 0) ? i_rf_in[47:40] + (w_f1_4 ^ i_rsk[23:16]):
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i_rf_in[47:40] - (w_f1_4 ^ i_rsk[15:8]);
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assign w_rf_mv[1] = (i_op == 0) ? i_rf_in[31:24] ^ (w_f0_2 + i_rsk[15:8]):
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i_rf_in[31:24] ^ (w_f0_2 + i_rsk[23:16]);
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assign w_rf_mv[0] = (i_op == 0) ? i_rf_in[15:8] + (w_f1_0 ^ i_rsk[7:0]):
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i_rf_in[15:8] - (w_f1_0 ^ i_rsk[31:24]);
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assign w_rf_out7 = (i_rf_final == 1) ? w_rf_mv[3] :
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(i_op == 0) ? i_rf_in[55:48] :
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i_rf_in[7:0];
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assign w_rf_out6 = (i_rf_final == 1) ? i_rf_in[55:48] :
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(i_op == 0) ? w_rf_mv[2] :
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w_rf_mv[3];
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assign w_rf_out5 = (i_rf_final == 1) ? w_rf_mv[2] :
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(i_op == 0) ? i_rf_in[39:32] :
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i_rf_in[55:48];
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assign w_rf_out4 = (i_rf_final == 1) ? i_rf_in[39:32] :
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(i_op == 0) ? w_rf_mv[1] :
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w_rf_mv[2];
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assign w_rf_out3 = (i_rf_final == 1) ? w_rf_mv[1] :
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(i_op == 0) ? i_rf_in[23:16] :
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i_rf_in[39:32];
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assign w_rf_out2 = (i_rf_final == 1) ? i_rf_in[23:16] :
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(i_op == 0) ? w_rf_mv[0] :
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w_rf_mv[1];
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assign w_rf_out1 = (i_rf_final == 1) ? w_rf_mv[0] :
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(i_op == 0) ? i_rf_in[7:0] :
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i_rf_in[23:16];
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assign w_rf_out0 = (i_rf_final == 1) ? i_rf_in[7:0] :
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(i_op == 0) ? w_rf_mv[3] :
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w_rf_mv[0];
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assign w_rf_out = {w_rf_out7, w_rf_out6, w_rf_out5, w_rf_out4, w_rf_out3, w_rf_out2, w_rf_out1, w_rf_out0};
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assign o_rf_out = w_rf_out;
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endmodule
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