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[/] [hight/] [trunk/] [testbench/] [tb_HIGHT_CORE_TOP.v] - Blame information for rev 2

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1 2 truemind 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Testbench of top module for HIGHT Crypto Core               ////
4 
////                                                              ////
5 
////  This file is part of the HIGHT Crypto Core project          ////
6 
////  http://github.com/OpenSoCPlus/hight_crypto_core             ////
7 
////  http://www.opencores.org/project,hight                      ////
8 
////                                                              ////
9 
////  Description                                                 ////
10 
////  __description__                                             ////
11 
////                                                              ////
12 
////  Author(s):                                                  ////
13 
////      - JoonSoo Ha, json.ha@gmail.com                         ////
14 
////      - Younjoo Kim, younjookim.kr@gmail.com                  ////
15 
////                                                              ////
16 
//////////////////////////////////////////////////////////////////////
17 
////                                                              ////
18 
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG    ////
19 
////                                                              ////
20 
//// This source file may be used and distributed without         ////
21 
//// restriction provided that this copyright statement is not    ////
22 
//// removed from the file and that any derivative work contains  ////
23 
//// the original copyright notice and the associated disclaimer. ////
24 
////                                                              ////
25 
//// This source file is free software; you can redistribute it   ////
26 
//// and/or modify it under the terms of the GNU Lesser General   ////
27 
//// Public License as published by the Free Software Foundation; ////
28 
//// either version 2.1 of the License, or (at your option) any   ////
29 
//// later version.                                               ////
30 
////                                                              ////
31 
//// This source is distributed in the hope that it will be       ////
32 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35 
//// details.                                                     ////
36 
////                                                              ////
37 
//// You should have received a copy of the GNU Lesser General    ////
38 
//// Public License along with this source; if not, download it   ////
39 
//// from http://www.opencores.org/lgpl.shtml                     ////
40 
////                                                              ////
41 
//////////////////////////////////////////////////////////////////////
42 
 
43 
`timescale 1ns/1ps
44 
 
45 
module tb_HIGHT_CORE_TOP;
46 
 
47 
event do_finish;
48 
 
49 
//=====================================
50 
//
51 
//          PARAMETERS
52 
//
53 
//=====================================
54 
parameter HP_CLK = 5; // Half period of Clock
55 
 
56 
 
57 
//=====================================
58 
//
59 
//          I/O PORTS
60 
//
61 
//=====================================
62 
reg        rstn         ;
63 
reg        clk          ;
64 
 
65 
reg        i_mk_rdy     ;
66 
reg[127:0] i_mk         ;
67 
 
68 
reg        i_post_rdy   ;
69 
 
70 
reg        i_op         ;
71 
 
72 
reg        i_text_val   ;
73 
reg[63:0]  i_text_in    ;
74 
 
75 
wire       o_text_done  ;
76 
wire[63:0] o_text_out   ;
77 
 
78 
wire       o_rdy        ;
79 
 
80 
 
81 
//=====================================
82 
//
83 
//          PORT MAPPING
84 
//
85 
//=====================================
86 
// uut
87 
HIGHT_CORE_TOP uut_HIGHT_CORE_TOP(
88 
        .rstn        (rstn       ) ,
89 
        .clk         (clk        ) ,
90 
 
91 
        .i_mk_rdy    (i_mk_rdy   ) ,
92 
        .i_mk        (i_mk       ) ,
93 
 
94 
        .i_post_rdy  (i_post_rdy ) ,
95 
 
96 
        .i_op        (i_op       ) ,
97 
 
98 
        .i_text_val  (i_text_val ) ,
99 
        .i_text_in   (i_text_in  ) ,
100 
 
101 
        .o_text_done (o_text_done) ,
102 
        .o_text_out  (o_text_out ) ,
103 
 
104 
        .o_rdy       (o_rdy      )
105 
);
106 
 
107 
 
108 
//=====================================
109 
//
110 
//          STIMULUS
111 
//
112 
//=====================================
113 
// clock generation
114 
initial begin
115 
        clk = 1'b0;
116 
        forever clk = #(HP_CLK) ~clk;
117 
end
118 
 
119 
// reset generation
120 
initial begin
121 
        rstn = 1'b1;
122 
        @(posedge clk);
123 
        @(negedge clk);
124 
        rstn = 1'b0;
125 
        repeat(2) @(negedge clk);
126 
        rstn = 1'b1;
127 
end
128 
 
129 
// input generation
130 
initial begin
131 
        $display("===== SIM START =====");
132 
        // insert your code
133 
 
134 
        /******** Encryption w/ test vectr 1 *******/
135 
        // initial input value
136 
        i_mk_rdy   = 1'b1;
137 
        i_mk       = 128'h0011_2233_4455_6677_8899_aabb_ccdd_eeff;
138 
        i_op       = 1'b0;
139 
        i_post_rdy = 1'b1;
140 
        i_text_val = 1'b0;
141 
        i_text_in  = 64'h0000_0000_0000_0000;
142 
 
143 
        // reset time
144 
        @(negedge rstn);
145 
        @(posedge rstn);
146 
        @(negedge clk);
147 
 
148 
        // Key Config Phase
149 
        @(negedge clk);
150 
        i_mk_rdy  = 1'b0;
151 
        repeat(4) @(posedge clk);
152 
        @(negedge clk);
153 
        i_mk_rdy = 1'b1;
154 
 
155 
        //// first ciphering ////
156 
        // insert 2 clock delay
157 
        @(posedge clk);
158 
        repeat(2) @(posedge clk);
159 
 
160 
        // insert text
161 
        @(negedge clk);
162 
        i_text_val = 1'b1;
163 
        @(negedge clk);
164 
        i_text_val = 1'b0;
165 
 
166 
        // wait text done
167 
        wait(o_text_done)
168 
        @(posedge clk);
169 
 
170 
        // post rdy inactive
171 
        @(negedge clk);
172 
        i_post_rdy = 1'b0;
173 
 
174 
 
175 
        //// second ciphering ////
176 
        // insert text
177 
        @(negedge clk);
178 
        i_text_val = 1'b1;
179 
        @(negedge clk);
180 
        i_text_val = 1'b0;
181 
 
182 
        // wait done state
183 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
184 
        @(posedge clk);
185 
 
186 
        // insert 3clk delay
187 
        repeat(3) @(posedge clk);
188 
 
189 
        // post rdy active
190 
        i_post_rdy = 1'b1;
191 
 
192 
        // delay
193 
        repeat(10) @(posedge clk);
194 
 
195 
 
196 
 
197 
        /******** Decryption w/ test vectr 1 *******/
198 
        // initial input value
199 
        i_mk_rdy   = 1'b1;
200 
        i_mk       = 128'h0011_2233_4455_6677_8899_aabb_ccdd_eeff;
201 
        i_op       = 1'b1;
202 
        i_post_rdy = 1'b1;
203 
        i_text_val = 1'b0;
204 
        i_text_in  = 64'h00f4_18ae_d94f_03f2;
205 
 
206 
        // Key Config Phase
207 
        @(negedge clk);
208 
        i_mk_rdy  = 1'b0;
209 
        repeat(4) @(posedge clk);
210 
        @(negedge clk);
211 
        i_mk_rdy = 1'b1;
212 
 
213 
        //// first ciphering ////
214 
        // insert 2 clock delay
215 
        @(posedge clk);
216 
        repeat(2) @(posedge clk);
217 
 
218 
        // insert text
219 
        @(negedge clk);
220 
        i_text_val = 1'b1;
221 
        @(negedge clk);
222 
        i_text_val = 1'b0;
223 
 
224 
        // wait text done
225 
        wait(o_text_done)
226 
        @(posedge clk);
227 
 
228 
        // post rdy inactive
229 
        @(negedge clk);
230 
        i_post_rdy = 1'b0;
231 
 
232 
 
233 
        //// second ciphering ////
234 
        // insert text
235 
        @(negedge clk);
236 
        i_text_val = 1'b1;
237 
        @(negedge clk);
238 
        i_text_val = 1'b0;
239 
 
240 
        // wait done state
241 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
242 
        @(posedge clk);
243 
 
244 
        // insert 3clk delay
245 
        repeat(3) @(posedge clk);
246 
 
247 
        // post rdy active
248 
        i_post_rdy = 1'b1;
249 
 
250 
        // delay
251 
        repeat(20) @(posedge clk);
252 
 
253 
 
254 
 
255 
        /******** Encryption w/ test vectr 2 *******/
256 
        // initial input value
257 
        i_mk_rdy   = 1'b1;
258 
        i_mk       = 128'hffee_ddcc_bbaa_9988_7766_5544_3322_1100;
259 
        i_op       = 1'b0;
260 
        i_post_rdy = 1'b1;
261 
        i_text_val = 1'b0;
262 
        i_text_in  = 64'h0011_2233_4455_6677;
263 
 
264 
        // Key Config Phase
265 
        @(negedge clk);
266 
        i_mk_rdy  = 1'b0;
267 
        repeat(4) @(posedge clk);
268 
        @(negedge clk);
269 
        i_mk_rdy = 1'b1;
270 
 
271 
        //// first ciphering ////
272 
        // insert 2 clock delay
273 
        @(posedge clk);
274 
        repeat(2) @(posedge clk);
275 
 
276 
        // insert text
277 
        @(negedge clk);
278 
        i_text_val = 1'b1;
279 
        @(negedge clk);
280 
        i_text_val = 1'b0;
281 
 
282 
        // wait text done
283 
        wait(o_text_done)
284 
        @(posedge clk);
285 
 
286 
        // post rdy inactive
287 
        @(negedge clk);
288 
        i_post_rdy = 1'b0;
289 
 
290 
 
291 
        //// second ciphering ////
292 
        // insert text
293 
        @(negedge clk);
294 
        i_text_val = 1'b1;
295 
        @(negedge clk);
296 
        i_text_val = 1'b0;
297 
 
298 
        // wait done state
299 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
300 
        @(posedge clk);
301 
 
302 
        // insert 3clk delay
303 
        repeat(3) @(posedge clk);
304 
 
305 
        // post rdy active
306 
        i_post_rdy = 1'b1;
307 
 
308 
        // delay
309 
        repeat(10) @(posedge clk);
310 
 
311 
 
312 
 
313 
        /******** Decryption w/ test vectr 2 *******/
314 
        // initial input value
315 
        i_mk_rdy   = 1'b1;
316 
        i_mk       = 128'hffee_ddcc_bbaa_9988_7766_5544_3322_1100;
317 
        i_op       = 1'b1;
318 
        i_post_rdy = 1'b1;
319 
        i_text_val = 1'b0;
320 
        i_text_in  = 64'h23ce_9f72_e543_e6d8;
321 
 
322 
        // Key Config Phase
323 
        @(negedge clk);
324 
        i_mk_rdy  = 1'b0;
325 
        repeat(4) @(posedge clk);
326 
        @(negedge clk);
327 
        i_mk_rdy = 1'b1;
328 
 
329 
        //// first ciphering ////
330 
        // insert 2 clock delay
331 
        @(posedge clk);
332 
        repeat(2) @(posedge clk);
333 
 
334 
        // insert text
335 
        @(negedge clk);
336 
        i_text_val = 1'b1;
337 
        @(negedge clk);
338 
        i_text_val = 1'b0;
339 
 
340 
        // wait text done
341 
        wait(o_text_done)
342 
        @(posedge clk);
343 
 
344 
        // post rdy inactive
345 
        @(negedge clk);
346 
        i_post_rdy = 1'b0;
347 
 
348 
 
349 
        //// second ciphering ////
350 
        // insert text
351 
        @(negedge clk);
352 
        i_text_val = 1'b1;
353 
        @(negedge clk);
354 
        i_text_val = 1'b0;
355 
 
356 
        // wait done state
357 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
358 
        @(posedge clk);
359 
 
360 
        // insert 3clk delay
361 
        repeat(3) @(posedge clk);
362 
 
363 
        // post rdy active
364 
        i_post_rdy = 1'b1;
365 
 
366 
        // delay
367 
        repeat(20) @(posedge clk);
368 
 
369 
 
370 
        /******** Encryption w/ test vectr 3 *******/
371 
        // initial input value
372 
        i_mk_rdy   = 1'b1;
373 
        i_mk       = 128'h0001_0203_0405_0607_0809_0a0b_0c0d_0e0f;
374 
        i_op       = 1'b0;
375 
        i_post_rdy = 1'b1;
376 
        i_text_val = 1'b0;
377 
        i_text_in  = 64'h0123_4567_89ab_cdef;
378 
 
379 
        // Key Config Phase
380 
        @(negedge clk);
381 
        i_mk_rdy  = 1'b0;
382 
        repeat(4) @(posedge clk);
383 
        @(negedge clk);
384 
        i_mk_rdy = 1'b1;
385 
 
386 
        //// first ciphering ////
387 
        // insert 2 clock delay
388 
        @(posedge clk);
389 
        repeat(2) @(posedge clk);
390 
 
391 
        // insert text
392 
        @(negedge clk);
393 
        i_text_val = 1'b1;
394 
        @(negedge clk);
395 
        i_text_val = 1'b0;
396 
 
397 
        // wait text done
398 
        wait(o_text_done)
399 
        @(posedge clk);
400 
 
401 
        // post rdy inactive
402 
        @(negedge clk);
403 
        i_post_rdy = 1'b0;
404 
 
405 
 
406 
        //// second ciphering ////
407 
        // insert text
408 
        @(negedge clk);
409 
        i_text_val = 1'b1;
410 
        @(negedge clk);
411 
        i_text_val = 1'b0;
412 
 
413 
        // wait done state
414 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
415 
        @(posedge clk);
416 
 
417 
        // insert 3clk delay
418 
        repeat(3) @(posedge clk);
419 
 
420 
        // post rdy active
421 
        i_post_rdy = 1'b1;
422 
 
423 
        // delay
424 
        repeat(10) @(posedge clk);
425 
 
426 
 
427 
 
428 
        /******** Decryption w/ test vectr 3 *******/
429 
        // initial input value
430 
        i_mk_rdy   = 1'b1;
431 
        i_mk       = 128'h0001_0203_0405_0607_0809_0a0b_0c0d_0e0f;
432 
        i_op       = 1'b1;
433 
        i_post_rdy = 1'b1;
434 
        i_text_val = 1'b0;
435 
        i_text_in  = 64'h7a6f_b2a2_8d23_f466;
436 
 
437 
        // Key Config Phase
438 
        @(negedge clk);
439 
        i_mk_rdy  = 1'b0;
440 
        repeat(4) @(posedge clk);
441 
        @(negedge clk);
442 
        i_mk_rdy = 1'b1;
443 
 
444 
        //// first ciphering ////
445 
        // insert 2 clock delay
446 
        @(posedge clk);
447 
        repeat(2) @(posedge clk);
448 
 
449 
        // insert text
450 
        @(negedge clk);
451 
        i_text_val = 1'b1;
452 
        @(negedge clk);
453 
        i_text_val = 1'b0;
454 
 
455 
        // wait text done
456 
        wait(o_text_done)
457 
        @(posedge clk);
458 
 
459 
        // post rdy inactive
460 
        @(negedge clk);
461 
        i_post_rdy = 1'b0;
462 
 
463 
 
464 
        //// second ciphering ////
465 
        // insert text
466 
        @(negedge clk);
467 
        i_text_val = 1'b1;
468 
        @(negedge clk);
469 
        i_text_val = 1'b0;
470 
 
471 
        // wait done state
472 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
473 
        @(posedge clk);
474 
 
475 
        // insert 3clk delay
476 
        repeat(3) @(posedge clk);
477 
 
478 
        // post rdy active
479 
        i_post_rdy = 1'b1;
480 
 
481 
        // delay
482 
        repeat(20) @(posedge clk);
483 
 
484 
        /******** Encryption w/ test vectr 4 *******/
485 
        // initial input value
486 
        i_mk_rdy   = 1'b1;
487 
        i_mk       = 128'h28db_c3bc_49ff_d87d_cfa5_09b1_1d42_2be7;
488 
        i_op       = 1'b0;
489 
        i_post_rdy = 1'b1;
490 
        i_text_val = 1'b0;
491 
        i_text_in  = 64'hb41e_6be2_eba8_4a14;
492 
 
493 
        // Key Config Phase
494 
        @(negedge clk);
495 
        i_mk_rdy  = 1'b0;
496 
        repeat(4) @(posedge clk);
497 
        @(negedge clk);
498 
        i_mk_rdy = 1'b1;
499 
 
500 
        //// first ciphering ////
501 
        // insert 2 clock delay
502 
        @(posedge clk);
503 
        repeat(2) @(posedge clk);
504 
 
505 
        // insert text
506 
        @(negedge clk);
507 
        i_text_val = 1'b1;
508 
        @(negedge clk);
509 
        i_text_val = 1'b0;
510 
 
511 
        // wait text done
512 
        wait(o_text_done)
513 
        @(posedge clk);
514 
 
515 
        // post rdy inactive
516 
        @(negedge clk);
517 
        i_post_rdy = 1'b0;
518 
 
519 
 
520 
        //// second ciphering ////
521 
        // insert text
522 
        @(negedge clk);
523 
        i_text_val = 1'b1;
524 
        @(negedge clk);
525 
        i_text_val = 1'b0;
526 
 
527 
        // wait done state
528 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
529 
        @(posedge clk);
530 
 
531 
        // insert 3clk delay
532 
        repeat(3) @(posedge clk);
533 
 
534 
        // post rdy active
535 
        i_post_rdy = 1'b1;
536 
 
537 
        // delay
538 
        repeat(10) @(posedge clk);
539 
 
540 
 
541 
 
542 
        /******** Decryption w/ test vectr 4 *******/
543 
        // initial input value
544 
        i_mk_rdy   = 1'b1;
545 
        i_mk       = 128'h28db_c3bc_49ff_d87d_cfa5_09b1_1d42_2be7;
546 
        i_op       = 1'b1;
547 
        i_post_rdy = 1'b1;
548 
        i_text_val = 1'b0;
549 
        i_text_in  = 64'hcc04_7a75_209c_1fc6;
550 
 
551 
        // Key Config Phase
552 
        @(negedge clk);
553 
        i_mk_rdy  = 1'b0;
554 
        repeat(4) @(posedge clk);
555 
        @(negedge clk);
556 
        i_mk_rdy = 1'b1;
557 
 
558 
        //// first ciphering ////
559 
        // insert 2 clock delay
560 
        @(posedge clk);
561 
        repeat(2) @(posedge clk);
562 
 
563 
        // insert text
564 
        @(negedge clk);
565 
        i_text_val = 1'b1;
566 
        @(negedge clk);
567 
        i_text_val = 1'b0;
568 
 
569 
        // wait text done
570 
        wait(o_text_done)
571 
        @(posedge clk);
572 
 
573 
        // post rdy inactive
574 
        @(negedge clk);
575 
        i_post_rdy = 1'b0;
576 
 
577 
 
578 
        //// second ciphering ////
579 
        // insert text
580 
        @(negedge clk);
581 
        i_text_val = 1'b1;
582 
        @(negedge clk);
583 
        i_text_val = 1'b0;
584 
 
585 
        // wait done state
586 
        wait(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate == uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE)
587 
        @(posedge clk);
588 
 
589 
        // insert 3clk delay
590 
        repeat(3) @(posedge clk);
591 
 
592 
        // post rdy active
593 
        i_post_rdy = 1'b1;
594 
 
595 
        // delay
596 
        repeat(10) @(posedge clk);
597 
        -> do_finish;
598 
end
599 
 
600 
// state monitoring
601 
reg[20*8:1] state;
602 
always @(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate) begin
603 
        case(uut_HIGHT_CORE_TOP.u_CONTROL.r_pstate)
604 
        uut_HIGHT_CORE_TOP.u_CONTROL.S_IDLE        : state <= "IDLE      ";
605 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_KEY_CONFIG  : state <= "KEY_CONFIG";
606 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RDY         : state <= "RDY       ";
607 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_WF1         : state <= "WF1       ";
608 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF1         : state <= "RF1       ";
609 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF2         : state <= "RF2       ";
610 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF3         : state <= "RF3       ";
611 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF4         : state <= "RF4       ";
612 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF5         : state <= "RF5       ";
613 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF6         : state <= "RF6       ";
614 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF7         : state <= "RF7       ";
615 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF8         : state <= "RF8       ";
616 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF9         : state <= "RF9       ";
617 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF10        : state <= "RF10      ";
618 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF11        : state <= "RF11      ";
619 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF12        : state <= "RF12      ";
620 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF13        : state <= "RF13      ";
621 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF14        : state <= "RF14      ";
622 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF15        : state <= "RF15      ";
623 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF16        : state <= "RF16      ";
624 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF17        : state <= "RF17      ";
625 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF18        : state <= "RF18      ";
626 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF19        : state <= "RF19      ";
627 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF20        : state <= "RF20      ";
628 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF21        : state <= "RF21      ";
629 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF22        : state <= "RF22      ";
630 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF23        : state <= "RF23      ";
631 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF24        : state <= "RF24      ";
632 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF25        : state <= "RF25      ";
633 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF26        : state <= "RF26      ";
634 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF27        : state <= "RF27      ";
635 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF28        : state <= "RF28      ";
636 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF29        : state <= "RF29      ";
637 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF30        : state <= "RF30      ";
638 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF31        : state <= "RF31      ";
639 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_RF32        : state <= "RF32      ";
640 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_DONE        : state <= "DONE      ";
641 
    uut_HIGHT_CORE_TOP.u_CONTROL.S_ERROR       : state <= "ERROR     ";
642 
        endcase
643 
end
644 
 
645 
// finish
646 
initial begin
647 
        @do_finish
648 
        $finish;
649 
end
650 
 
651 
// vcd dump
652 
initial begin
653 
        $dumpfile("dump/sim_tb_HIGHT_CORE_TOP.vcd");
654 
        $dumpvars(0, tb_HIGHT_CORE_TOP);
655 
end
656 
 
657 
endmodule
658 
 
659 
 

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