OpenCores
URL https://opencores.org/ocsvn/hive/hive/trunk

Subversion Repositories hive

[/] [hive/] [trunk/] [v01.09/] [boot_code/] [boot_code_log2.h] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ericw 
/*
2 
--------------------------------------------------------------------------------
3 
 
4 
Module : boot_code.h
5 
 
6 
--------------------------------------------------------------------------------
7 
 
8 
Function:
9 
- Boot code for a processor core.
10 
 
11 
Instantiates:
12 
- Nothing.
13 
 
14 
Notes:
15 
- For testing (@ core.v):
16 
  CLR_BASE              = 'h0;
17 
  CLR_SPAN              = 2;  // gives 4 instructions
18 
  INTR_BASE             = 'h20;  // 'd32
19 
  INTR_SPAN             = 2;  // gives 4 instructions
20 
 
21 
 
22 
--------------------------------------------------------------------------------
23 
*/
24 
 
25 
        /*
26 
        -------------------------
27 
        -- external parameters --
28 
        -------------------------
29 
        */
30 
        `include "op_encode.h"
31 
        `include "reg_set_addr.h"
32 
 
33 
        /*
34 
        ------------------------------------------------------------
35 
        -- defines that make programming code more human readable --
36 
        ------------------------------------------------------------
37 
        */
38 
        `define s0                              2'd0
39 
        `define s1                              2'd1
40 
        `define s2                              2'd2
41 
        `define s3                              2'd3
42 
        `define _                               1'b0
43 
        `define P                               1'b1
44 
        //
45 
        `define op_rd_i         op_rd_i[9:4]
46 
        `define op_rd_ix                op_rd_ix[9:4]
47 
        `define op_wr_i         op_wr_i[9:4]
48 
        `define op_wr_ix                op_wr_ix[9:4]
49 
        //
50 
        `define op_jmp_ie               op_jmp_ie[9:5]
51 
        `define op_jmp_iez      op_jmp_iez[9:5]
52 
        `define op_jmp_il               op_jmp_il[9:5]
53 
        `define op_jmp_ilz      op_jmp_ilz[9:5]
54 
        `define op_jmp_ile      op_jmp_ile[9:5]
55 
        `define op_jmp_ilez     op_jmp_ilez[9:5]
56 
        `define op_jmp_iug      op_jmp_iug[9:5]
57 
        `define op_jmp_igz      op_jmp_igz[9:5]
58 
        `define op_jmp_iuge     op_jmp_iuge[9:5]
59 
        `define op_jmp_igez     op_jmp_igez[9:5]
60 
        `define op_jmp_igl      op_jmp_igl[9:5]
61 
        `define op_jmp_iglz     op_jmp_iglz[9:5]
62 
        //
63 
        `define op_jmp_i                op_jmp_i[9:6]
64 
        //
65 
        `define op_byt_i                op_byt_i[9:8]
66 
        //
67 
        `define op_shl_i                op_shl_i[9:6]
68 
        `define op_shl_iu               op_shl_iu[9:6]
69 
        //
70 
        `define op_add_i                op_add_i[9:6]
71 
 
72 
        /*
73 
        ----------------------------------------
74 
        -- initialize: fill with default data --
75 
        ----------------------------------------
76 
        */
77 
        integer i;
78 
 
79 
        initial begin
80 
 
81 
/*      // fill with nop (some compilers need this)
82 
        for ( i = 0; i < CAPACITY; i = i+1 ) begin
83 
                ram[i] = { op_nop, `_, `_, `s0, `s0 };
84 
        end
85 
*/
86 
 
87 
        /*
88 
        ---------------
89 
        -- boot code --
90 
        ---------------
91 
        */
92 
 
93 
 
94 
        /*
95 
        ------------
96 
        -- TEST 0 --
97 
        ------------
98 
        */
99 
 
100 
        // Log base 2
101 
        // Thread 0 : Get input 32 bit GPIO, calculate log2, output 32 bit GPIO.
102 
        // Other threads : do nothing, loop forever
103 
 
104 
        ///////////////
105 
        // clr space //
106 
        ///////////////
107 
 
108 
        i='h0;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s1 };  // lit => s1
109 
        i=i+1;   ram[i] = 16'h040                                     ;  // addr
110 
        i=i+1;   ram[i] = {  op_gto,                `P, `_, `s1, `s0 };  // goto, pop s1 (addr)
111 
        //
112 
        i='h4;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
113 
        i=i+4;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
114 
        i=i+4;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
115 
        i=i+4;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
116 
        i=i+4;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
117 
        i=i+4;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
118 
        i=i+4;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
119 
 
120 
        ////////////////
121 
        // intr space //
122 
        ////////////////
123 
 
124 
        ///////////////////////
125 
        // code & data space //
126 
        ///////////////////////
127 
 
128 
        // read 32 bit GPIO data to s0
129 
        i='h40;  ram[i] = {  op_lit_u,              `_, `_, `s0, `s3 };  // lit => s3
130 
        i=i+1;   ram[i] = 16'h050                                     ;  // addr
131 
        i=i+1;   ram[i] = {  op_gsb,                `P, `_, `s3, `s3 };  // gsb, pop s3 (addr)
132 
 
133 
        // write s0 data to 32 bit GPIO
134 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s3 };  // lit => s3
135 
        i=i+1;   ram[i] = 16'h058                                     ;  // addr
136 
        i=i+1;   ram[i] = {  op_gsb,                `P, `_, `s3, `s3 };  // gsb, pop s3 (addr)
137 
 
138 
        // do log2 of s0
139 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s3 };  // lit => s3
140 
        i=i+1;   ram[i] = 16'h060                                     ;  // addr
141 
        i=i+1;   ram[i] = {  op_gsb,                `P, `_, `s3, `s3 };  // gsb, pop s3 (addr)
142 
 
143 
        // write s0 data to 32 bit GPIO
144 
        i=i+1;   ram[i] = {  op_lit_u,              `_, `_, `s0, `s3 };  // lit => s3
145 
        i=i+1;   ram[i] = 16'h058                                     ;  // addr
146 
        i=i+1;   ram[i] = {  op_gsb,                `P, `_, `s3, `s3 };  // gsb, pop s3 (addr)
147 
 
148 
        // loop forever
149 
        i=i+1;   ram[i] = { `op_jmp_i,       -6'h1, `_, `_, `s0, `s0 };  // loop forever
150 
 
151 
 
152 
 
153 
 
154 
        // sub : read 32 bit GPIO => s0, return to (s3)
155 
        i='h50;  ram[i] = {  op_lit_u,              `_, `_, `s0, `s1 };  // lit => s1
156 
        i=i+1;   ram[i] = REG_BASE_ADDR                               ;  // reg base addr
157 
        i=i+1;   ram[i] = { `op_rd_i,   IO_LO_ADDR, `_, `_, `s1, `s0 };  // read (s1+offset) => s0
158 
        i=i+1;   ram[i] = { `op_rd_ix,  IO_HI_ADDR, `P, `P, `s1, `s0 };  // read (s1+offset) => s0, pop s1 & s0
159 
        i=i+1;   ram[i] = {  op_gto,                `P, `_, `s3, `s0 };  // return, pop s3
160 
 
161 
 
162 
        // sub : write s0 => 32 bit GPIO, return to (s3)
163 
        i='h58;  ram[i] = {  op_lit_u,              `_, `_, `s0, `s1 };  // lit => s1
164 
        i=i+1;   ram[i] = REG_BASE_ADDR                               ;  // reg base addr
165 
        i=i+1;   ram[i] = { `op_wr_i,   IO_LO_ADDR, `_, `_, `s1, `s0 };  // write s0 => (s1+offset)
166 
        i=i+1;   ram[i] = { `op_wr_ix,  IO_HI_ADDR, `P, `_, `s1, `s0 };  // write s0 => (s1+offset), pop s1
167 
        i=i+1;   ram[i] = {  op_gto,                `P, `_, `s3, `s0 };  // return, pop s3
168 
 
169 
 
170 
        // sub : log2(s0)=>s0, return to (s3)
171 
        //
172 
        // s0 : input, normalize, square, output
173 
        // s1 : characteristic (5 MSBs of output) and mantissa (27 LSBs of output)
174 
        // s2 : loop index
175 
        // s3 : subroutine return address
176 
        //
177 
        // input 0 is an error, return
178 
        i='h60;  ram[i] = { `op_jmp_iglz,    5'd1,  `_, `_, `s0, `s0 };  // (s0!==0) ? skip return
179 
        i=i+1;   ram[i] = {  op_gto,                `P, `_, `s3, `s0 };  // return to (s3), pop s3
180 
        // normalize binary search
181 
        i=i+1;   ram[i] = { `op_byt_i,       8'd31, `_, `_, `s0, `s1 };  // 31=>s1, characteristic
182 
        //
183 
        i=i+1;   ram[i] = { `op_shl_iu,     -6'd16, `_, `_, `s0, `s0 };  // s0>>16=>s0
184 
        i=i+1;   ram[i] = { `op_jmp_iglz,     5'd2, `_, `P, `s0, `s0 };  // (s0<>0) ? jump, pop s0
185 
        i=i+1;   ram[i] = { `op_shl_i,       6'd16, `_, `P, `s0, `s0 };  // s0<<16=>s0, pop s0
186 
        i=i+1;   ram[i] = { `op_add_i,      -6'd16, `_, `P, `s0, `s1 };  // s1-16=>s1, pop s1
187 
        //
188 
        i=i+1;   ram[i] = { `op_shl_iu,     -6'd24, `_, `_, `s0, `s0 };  // s0>>24=>s0
189 
        i=i+1;   ram[i] = { `op_jmp_iglz,     5'd2, `_, `P, `s0, `s0 };  // (s0<>0) ? jump, pop s0
190 
        i=i+1;   ram[i] = { `op_shl_i,        6'd8, `_, `P, `s0, `s0 };  // s0<<8=>s0, pop s0
191 
        i=i+1;   ram[i] = { `op_add_i,       -6'd8, `_, `P, `s0, `s1 };  // s1-8=>s1, pop s1
192 
        //
193 
        i=i+1;   ram[i] = { `op_shl_iu,     -6'd28, `_, `_, `s0, `s0 };  // s0>>28=>s0
194 
        i=i+1;   ram[i] = { `op_jmp_iglz,     5'd2, `_, `P, `s0, `s0 };  // (s0<>0) ? jump, pop s0
195 
        i=i+1;   ram[i] = { `op_shl_i,        6'd4, `_, `P, `s0, `s0 };  // s0<<4=>s0, pop s0
196 
        i=i+1;   ram[i] = { `op_add_i,       -6'd4, `_, `P, `s0, `s1 };  // s1-4=>s1, pop s1
197 
        //
198 
        i=i+1;   ram[i] = { `op_shl_iu,     -6'd30, `_, `_, `s0, `s0 };  // s0>>30=>s0
199 
        i=i+1;   ram[i] = { `op_jmp_iglz,     5'd2, `_, `P, `s0, `s0 };  // (s0<>0) ? jump, pop s0
200 
        i=i+1;   ram[i] = { `op_shl_i,        6'd2, `_, `P, `s0, `s0 };  // s0<<2=>s0, pop s0
201 
        i=i+1;   ram[i] = { `op_add_i,       -6'd2, `_, `P, `s0, `s1 };  // s1-2=>s1, pop s1
202 
        //
203 
        i=i+1;   ram[i] = { `op_jmp_ilz,      5'd2, `_, `_, `s0, `s0 };  // (s0<0) ? jump
204 
        i=i+1;   ram[i] = { `op_shl_i,        6'd1, `_, `P, `s0, `s0 };  // s0<<1=>s0, pop s0
205 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s1 };  // s1-1=>s1, pop s1
206 
        // loop setup
207 
        i=i+1;   ram[i] = { `op_byt_i,       8'd27, `_, `_, `s0, `s2 };  // 27=>s2
208 
        // square loop
209 
        i=i+1;   ram[i] = { `op_add_i,       -6'd1, `_, `P, `s0, `s2 };  // s2--=>s2, pop s2
210 
        i=i+1;   ram[i] = { `op_shl_i,        6'd1, `_, `P, `s0, `s1 };  // s1<<1=>s1, pop s1
211 
        i=i+1;   ram[i] = {  op_mul_ux,             `_, `P, `s0, `s0 };  // s0*s0=>s0, pop s0
212 
        i=i+1;   ram[i] = { `op_jmp_igez,     5'd2, `_, `_, `s0, `s0 };  // (s0[31]==0) ? jump
213 
        i=i+1;   ram[i] = { `op_add_i,        6'd1, `_, `P, `s0, `s1 };  // s1++=>s1, pop s1
214 
        i=i+1;   ram[i] = { `op_jmp_i,        6'd1, `_, `_, `s0, `s0 };  // skip
215 
        i=i+1;   ram[i] = { `op_shl_i,        6'd1, `_, `P, `s0, `s0 };  // s0<<1=>s0, pop s0
216 
        i=i+1;   ram[i] = { `op_jmp_igz,     -5'd8, `_, `_, `s3, `s2 };  // (s2>0) ? do again
217 
        // s1=>s0; cleanup, return
218 
        i=i+1;   ram[i] = {  op_cpy,                `P, `P, `s1, `s0 };  // s1=>s0, pop both
219 
        i=i+1;   ram[i] = {  op_gto,                `P, `P, `s3, `s2 };  // return, pop s3 & s2
220 
        // end sub
221 
 
222 
 
223 
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.