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[/] [hive/] [trunk/] [v01.09/] [control_ring.v] - Blame information for rev 2

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1 2 ericw
/*
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--------------------------------------------------------------------------------
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Module : control_ring.v
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--------------------------------------------------------------------------------
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Function:
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- Processor control path.
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Instantiates:
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- (1x) thread_ring.v
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- (2x) event_ctrl.v
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- (1x) cond_test.v
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- (1x) op_decode.v
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- (1x) pc_ring.v
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Notes:
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- 8 stage data pipeline consisting of several storage rings.
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--------------------------------------------------------------------------------
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*/
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module control_ring
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        #(
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        parameter       integer                                                 DATA_W                  = 32,           // data width
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        parameter       integer                                                 ADDR_W                  = 16,           // address width
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        parameter       integer                                                 THREADS                 = 8,            // threads
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        parameter       integer                                                 THRD_W                  = 3,            // thread width
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        parameter       integer                                                 STACKS                  = 4,            // number of stacks
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        parameter       integer                                                 STK_W                           = 2,            // stack selector width
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        parameter       integer                                                 IM_DATA_W               = 8,            // immediate data width
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        parameter       integer                                                 IM_ADDR_W               = 6,            // immediate data width
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        parameter       integer                                                 OP_CODE_W               = 16,           // opcode width
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        parameter       integer                                                 LG_W                            = 2,            // logical operation width
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        parameter       [ADDR_W-1:0]                                     CLR_BASE                        = 'h0,  // clear address base (concat)
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        parameter       integer                                                 CLR_SPAN                        = 0,             // clear address span (2^n)
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        parameter       [ADDR_W-1:0]                                     INTR_BASE               = 'h8,  // interrupt address base (concat)
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        parameter       integer                                                 INTR_SPAN               = 0              // interrupt address span (2^n)
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        )
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        (
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        // clocks & resets
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        input                   wire                                                            clk_i,                                          // clock
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        input                   wire                                                            rst_i,                                          // async. reset, active high
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        // control I/O
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        input                   wire    [THREADS-1:0]                    clr_req_i,                                      // clear request, active high
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        output          wire    [THREADS-1:0]                    clr_ack_o,                                      // clear ack, active high until serviced
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        input                   wire    [THREADS-1:0]                    intr_en_i,                                      // interrupt enable, active high
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        input                   wire    [THREADS-1:0]                    intr_req_i,                                     // interrupt request, active high
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        output          wire    [THREADS-1:0]                    intr_ack_o,                                     // interrupt ack, active high until serviced
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        input                   wire    [OP_CODE_W-1:0]          op_code_i,                                      // opcode
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        output          wire                                                            op_code_er_o,                           // 1=illegal op code encountered
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        // ALU I/O
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        input                   wire    [DATA_W/2-1:0]                   b_lo_i,                                         // b_lo
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        output          wire    [IM_DATA_W-1:0]          im_data_o,                                      // immediate data
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        output          wire    [STK_W-1:0]                              a_sel_o,                                                // stack selector
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        output          wire    [STK_W-1:0]                              b_sel_o,                                                // stack selector
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        output          wire                                                            imda_o,                                         // 1=immediate data
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        output          wire                                                            sgn_o,                                          // 1=signed
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        output          wire                                                            ext_o,                                          // 1=extended
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        output          wire    [LG_W-1:0]                               lg_o,                                                   // see decode in notes
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        output          wire                                                            add_o,                                          // 1=add
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        output          wire                                                            sub_o,                                          // 1=subtract
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        output          wire                                                            mul_o,                                          // 1=multiply
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        output          wire                                                            shl_o,                                          // 1=shift left
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        output          wire                                                            cpy_o,                                          // 1=copy b
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        output          wire                                                            dm_o,                                                   // 1=data mem
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        output          wire                                                            rtn_o,                                          // 1=return pc
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        output          wire                                                            rd_o,                                                   // 1=read
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        output          wire                                                            wr_o,                                                   // 1=write
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        // stack I/O
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        output          wire                                                            stk_clr_o,                                      // stacks clear
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        output          wire    [STACKS-1:0]                     pop_o,                                          // stacks pop
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        output          wire    [STACKS-1:0]                     push_o,                                         // stacks push
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        // flags
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        input                   wire                                                            nez_i,                                          //      a != 0
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        input                   wire                                                            ne_i,                                                   //      a != b
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        input                   wire                                                            ltz_i,                                          //      a < 0
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        input                   wire                                                            lt_i,                                                   //      a < b
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        // threads
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        output          wire    [THRD_W-1:0]                     thrd_0_o,
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        output          wire    [THRD_W-1:0]                     thrd_2_o,
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        output          wire    [THRD_W-1:0]                     thrd_3_o,
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        output          wire    [THRD_W-1:0]                     thrd_6_o,
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        // addresses
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        output          wire    [IM_ADDR_W-1:0]          im_addr_o,                                      // immediate address (offset)
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        output          wire    [ADDR_W-1:0]                     pc_1_o,
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        output          wire    [ADDR_W-1:0]                     pc_3_o,
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        output          wire    [ADDR_W-1:0]                     pc_4_o
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        );
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        /*
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        ----------------------
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        -- internal signals --
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        ----------------------
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        */
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        wire                                                                                            pc_clr, lit, jmp, gto, intr, imad, tst_2;
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        wire                                                                                            stk_clr;
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        wire                                    [STACKS-1:0]                     pop, push;
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        wire                                                                                            tst_eq, tst_lt, tst_gt, tst_ab;
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        wire                                                                                            thrd_clr, thrd_intr;
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        wire                                    [THRD_W-1:0]                     thrd_5;
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106
 
107
 
108
        /*
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        ================
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        == code start ==
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        ================
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        */
113
 
114
 
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        // establish threads
116
        thread_ring
117
        #(
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        .THRD_W                 ( THRD_W )
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        )
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        thread_ring
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .thrd_0_o               ( thrd_0_o ),
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        .thrd_1_o               (  ),
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        .thrd_2_o               ( thrd_2_o ),
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        .thrd_3_o               ( thrd_3_o ),
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        .thrd_4_o               (  ),
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        .thrd_5_o               ( thrd_5 ),
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        .thrd_6_o               ( thrd_6_o ),
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        .thrd_7_o               (  )
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        );
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        // handle external thread clear requests
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        event_ctrl
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        #(
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        .REGS_REQ               ( 0 ),  // don't resync
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        .EDGE_REQ               ( 1 ),  // edge sensitive
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        .RESET_VAL              ( { THREADS{ 1'b1 } } ),  // clear threads @ power-up
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        .THREADS                        ( THREADS ),
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        .THRD_W                 ( THRD_W )
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        )
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        clr_event_ctrl
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .thrd_i                 ( thrd_5 ),
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        .en_i                           ( { THREADS{ 1'b1 } } ),  // always enable
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        .req_i                  ( clr_req_i ),
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        .ack_o                  ( clr_ack_o ),
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        .event_o                        ( thrd_clr )
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        );
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        // handle external thread interrupt requests
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        event_ctrl
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        #(
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        .REGS_REQ               ( 2 ),  // resync
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        .EDGE_REQ               ( 1 ),  // edge sensitive
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        .RESET_VAL              ( 0 ),
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        .THREADS                        ( THREADS ),
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        .THRD_W                 ( THRD_W )
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        )
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        intr_event_ctrl
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .thrd_i                 ( thrd_5 ),
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        .en_i                           ( intr_en_i ),
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        .req_i                  ( intr_req_i ),
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        .ack_o                  ( intr_ack_o ),
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        .event_o                        ( thrd_intr )
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        );
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        // conditional jump etc. testing
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        cond_test
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        #(
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        .REGS_TST               ( 2 ),
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        .REGS_OUT               ( 0 )
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        )
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        cond_test
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .nez_i                  ( nez_i ),
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        .ne_i                           ( ne_i ),
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        .ltz_i                  ( ltz_i ),
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        .lt_i                           ( lt_i ),
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        .tst_eq_i               ( tst_eq ),
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        .tst_lt_i               ( tst_lt ),
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        .tst_gt_i               ( tst_gt ),
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        .tst_ab_i               ( tst_ab ),
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        .tst_o                  ( tst_2 )
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        );
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        // op_code decoding
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        op_decode
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        #(
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        .REGS_IN                        ( 0 ),
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        .REGS_OUT               ( 1 ),
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        .STACKS                 ( STACKS ),
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        .STK_W                  ( STK_W ),
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        .DATA_W                 ( DATA_W ),
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        .IM_DATA_W              ( IM_DATA_W ),
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        .IM_ADDR_W              ( IM_ADDR_W ),
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        .OP_CODE_W              ( OP_CODE_W ),
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        .LG_W                           ( LG_W )
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        )
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        op_decode
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .thrd_clr_i             ( thrd_clr ),
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        .thrd_intr_i    ( thrd_intr ),
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        .op_code_i              ( op_code_i ),
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        .op_code_er_o   ( op_code_er_o ),
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        .im_data_o              ( im_data_o ),
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        .im_addr_o              ( im_addr_o ),
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        .pc_clr_o               ( pc_clr ),
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        .lit_o                  ( lit ),
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        .jmp_o                  ( jmp ),
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        .gto_o                  ( gto ),
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        .intr_o                 ( intr ),
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        .tst_eq_o               ( tst_eq ),
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        .tst_lt_o               ( tst_lt ),
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        .tst_gt_o               ( tst_gt ),
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        .tst_ab_o               ( tst_ab ),
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        .stk_clr_o              ( stk_clr_o ),
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        .pop_o                  ( pop_o ),
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        .push_o                 ( push_o ),
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        .a_sel_o                        ( a_sel_o ),
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        .b_sel_o                        ( b_sel_o ),
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        .imda_o                 ( imda_o ),
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        .imad_o                 ( imad ),
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        .sgn_o                  ( sgn_o ),
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        .ext_o                  ( ext_o ),
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        .lg_o                           ( lg_o ),
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        .add_o                  ( add_o ),
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        .sub_o                  ( sub_o ),
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        .mul_o                  ( mul_o ),
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        .shl_o                  ( shl_o ),
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        .cpy_o                  ( cpy_o ),
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        .dm_o                           ( dm_o ),
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        .rtn_o                  ( rtn_o ),
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        .rd_o                           ( rd_o ),
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        .wr_o                           ( wr_o )
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        );
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        // pc generation & storage
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        pc_ring
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        #(
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        .THREADS                        ( THREADS ),
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        .THRD_W                 ( THRD_W ),
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        .DATA_W                 ( DATA_W ),
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        .ADDR_W                 ( ADDR_W ),
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        .IM_ADDR_W              ( IM_ADDR_W ),
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        .CLR_BASE               ( CLR_BASE ),
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        .CLR_SPAN               ( CLR_SPAN ),
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        .INTR_BASE              ( INTR_BASE ),
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        .INTR_SPAN              ( INTR_SPAN )
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        )
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        pc_ring
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        (
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        .clk_i                  ( clk_i ),
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        .rst_i                  ( rst_i ),
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        .thrd_0_i               ( thrd_0_o ),
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        .thrd_3_i               ( thrd_3_o ),
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        .clr_i                  ( pc_clr ),
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        .lit_i                  ( lit ),
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        .jmp_i                  ( jmp ),
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        .gto_i                  ( gto ),
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        .intr_i                 ( intr ),
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        .imad_i                 ( imad ),
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        .tst_2_i                        ( tst_2 ),
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        .b_lo_i                 ( b_lo_i ),
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        .im_addr_i              ( im_addr_o ),
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        .pc_0_o                 (  ),
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        .pc_1_o                 ( pc_1_o ),
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        .pc_2_o                 (  ),
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        .pc_3_o                 ( pc_3_o ),
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        .pc_4_o                 ( pc_4_o ),
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        .pc_5_o                 (  ),
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        .pc_6_o                 (  ),
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        .pc_7_o                 (  )
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        );
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endmodule

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