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[/] [hive/] [trunk/] [v01.09/] [control_ring.v] - Blame information for rev 2

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/*
--------------------------------------------------------------------------------
 
Module : control_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor control path.
 
Instantiates:
- (1x) thread_ring.v
- (2x) event_ctrl.v
- (1x) cond_test.v
- (1x) op_decode.v
- (1x) pc_ring.v
 
Notes:
- 8 stage data pipeline consisting of several storage rings.
 
--------------------------------------------------------------------------------
*/
 
module control_ring
        #(
        parameter       integer                                                 DATA_W                  = 32,           // data width
        parameter       integer                                                 ADDR_W                  = 16,           // address width
        parameter       integer                                                 THREADS                 = 8,            // threads
        parameter       integer                                                 THRD_W                  = 3,            // thread width
        parameter       integer                                                 STACKS                  = 4,            // number of stacks
        parameter       integer                                                 STK_W                           = 2,            // stack selector width
        parameter       integer                                                 IM_DATA_W               = 8,            // immediate data width
        parameter       integer                                                 IM_ADDR_W               = 6,            // immediate data width
        parameter       integer                                                 OP_CODE_W               = 16,           // opcode width
        parameter       integer                                                 LG_W                            = 2,            // logical operation width
        parameter       [ADDR_W-1:0]                                     CLR_BASE                        = 'h0,  // clear address base (concat)
        parameter       integer                                                 CLR_SPAN                        = 0,             // clear address span (2^n)
        parameter       [ADDR_W-1:0]                                     INTR_BASE               = 'h8,  // interrupt address base (concat)
        parameter       integer                                                 INTR_SPAN               = 0              // interrupt address span (2^n)
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire    [THREADS-1:0]                    clr_req_i,                                      // clear request, active high
        output          wire    [THREADS-1:0]                    clr_ack_o,                                      // clear ack, active high until serviced
        input                   wire    [THREADS-1:0]                    intr_en_i,                                      // interrupt enable, active high
        input                   wire    [THREADS-1:0]                    intr_req_i,                                     // interrupt request, active high
        output          wire    [THREADS-1:0]                    intr_ack_o,                                     // interrupt ack, active high until serviced
        input                   wire    [OP_CODE_W-1:0]          op_code_i,                                      // opcode
        output          wire                                                            op_code_er_o,                           // 1=illegal op code encountered
        // ALU I/O
        input                   wire    [DATA_W/2-1:0]                   b_lo_i,                                         // b_lo
        output          wire    [IM_DATA_W-1:0]          im_data_o,                                      // immediate data
        output          wire    [STK_W-1:0]                              a_sel_o,                                                // stack selector
        output          wire    [STK_W-1:0]                              b_sel_o,                                                // stack selector
        output          wire                                                            imda_o,                                         // 1=immediate data
        output          wire                                                            sgn_o,                                          // 1=signed
        output          wire                                                            ext_o,                                          // 1=extended
        output          wire    [LG_W-1:0]                               lg_o,                                                   // see decode in notes
        output          wire                                                            add_o,                                          // 1=add
        output          wire                                                            sub_o,                                          // 1=subtract
        output          wire                                                            mul_o,                                          // 1=multiply
        output          wire                                                            shl_o,                                          // 1=shift left
        output          wire                                                            cpy_o,                                          // 1=copy b
        output          wire                                                            dm_o,                                                   // 1=data mem
        output          wire                                                            rtn_o,                                          // 1=return pc
        output          wire                                                            rd_o,                                                   // 1=read
        output          wire                                                            wr_o,                                                   // 1=write
        // stack I/O
        output          wire                                                            stk_clr_o,                                      // stacks clear
        output          wire    [STACKS-1:0]                     pop_o,                                          // stacks pop
        output          wire    [STACKS-1:0]                     push_o,                                         // stacks push
        // flags
        input                   wire                                                            nez_i,                                          //      a != 0
        input                   wire                                                            ne_i,                                                   //      a != b
        input                   wire                                                            ltz_i,                                          //      a < 0
        input                   wire                                                            lt_i,                                                   //      a < b
        // threads
        output          wire    [THRD_W-1:0]                     thrd_0_o,
        output          wire    [THRD_W-1:0]                     thrd_2_o,
        output          wire    [THRD_W-1:0]                     thrd_3_o,
        output          wire    [THRD_W-1:0]                     thrd_6_o,
        // addresses
        output          wire    [IM_ADDR_W-1:0]          im_addr_o,                                      // immediate address (offset)
        output          wire    [ADDR_W-1:0]                     pc_1_o,
        output          wire    [ADDR_W-1:0]                     pc_3_o,
        output          wire    [ADDR_W-1:0]                     pc_4_o
        );
 
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                                                                            pc_clr, lit, jmp, gto, intr, imad, tst_2;
        wire                                                                                            stk_clr;
        wire                                    [STACKS-1:0]                     pop, push;
        wire                                                                                            tst_eq, tst_lt, tst_gt, tst_ab;
        wire                                                                                            thrd_clr, thrd_intr;
        wire                                    [THRD_W-1:0]                     thrd_5;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // establish threads
        thread_ring
        #(
        .THRD_W                 ( THRD_W )
        )
        thread_ring
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_0_o               ( thrd_0_o ),
        .thrd_1_o               (  ),
        .thrd_2_o               ( thrd_2_o ),
        .thrd_3_o               ( thrd_3_o ),
        .thrd_4_o               (  ),
        .thrd_5_o               ( thrd_5 ),
        .thrd_6_o               ( thrd_6_o ),
        .thrd_7_o               (  )
        );
 
 
        // handle external thread clear requests
        event_ctrl
        #(
        .REGS_REQ               ( 0 ),  // don't resync
        .EDGE_REQ               ( 1 ),  // edge sensitive
        .RESET_VAL              ( { THREADS{ 1'b1 } } ),  // clear threads @ power-up
        .THREADS                        ( THREADS ),
        .THRD_W                 ( THRD_W )
        )
        clr_event_ctrl
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_i                 ( thrd_5 ),
        .en_i                           ( { THREADS{ 1'b1 } } ),  // always enable
        .req_i                  ( clr_req_i ),
        .ack_o                  ( clr_ack_o ),
        .event_o                        ( thrd_clr )
        );
 
 
        // handle external thread interrupt requests
        event_ctrl
        #(
        .REGS_REQ               ( 2 ),  // resync
        .EDGE_REQ               ( 1 ),  // edge sensitive
        .RESET_VAL              ( 0 ),
        .THREADS                        ( THREADS ),
        .THRD_W                 ( THRD_W )
        )
        intr_event_ctrl
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_i                 ( thrd_5 ),
        .en_i                           ( intr_en_i ),
        .req_i                  ( intr_req_i ),
        .ack_o                  ( intr_ack_o ),
        .event_o                        ( thrd_intr )
        );
 
 
        // conditional jump etc. testing
        cond_test
        #(
        .REGS_TST               ( 2 ),
        .REGS_OUT               ( 0 )
        )
        cond_test
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .nez_i                  ( nez_i ),
        .ne_i                           ( ne_i ),
        .ltz_i                  ( ltz_i ),
        .lt_i                           ( lt_i ),
        .tst_eq_i               ( tst_eq ),
        .tst_lt_i               ( tst_lt ),
        .tst_gt_i               ( tst_gt ),
        .tst_ab_i               ( tst_ab ),
        .tst_o                  ( tst_2 )
        );
 
 
        // op_code decoding
        op_decode
        #(
        .REGS_IN                        ( 0 ),
        .REGS_OUT               ( 1 ),
        .STACKS                 ( STACKS ),
        .STK_W                  ( STK_W ),
        .DATA_W                 ( DATA_W ),
        .IM_DATA_W              ( IM_DATA_W ),
        .IM_ADDR_W              ( IM_ADDR_W ),
        .OP_CODE_W              ( OP_CODE_W ),
        .LG_W                           ( LG_W )
        )
        op_decode
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_clr_i             ( thrd_clr ),
        .thrd_intr_i    ( thrd_intr ),
        .op_code_i              ( op_code_i ),
        .op_code_er_o   ( op_code_er_o ),
        .im_data_o              ( im_data_o ),
        .im_addr_o              ( im_addr_o ),
        .pc_clr_o               ( pc_clr ),
        .lit_o                  ( lit ),
        .jmp_o                  ( jmp ),
        .gto_o                  ( gto ),
        .intr_o                 ( intr ),
        .tst_eq_o               ( tst_eq ),
        .tst_lt_o               ( tst_lt ),
        .tst_gt_o               ( tst_gt ),
        .tst_ab_o               ( tst_ab ),
        .stk_clr_o              ( stk_clr_o ),
        .pop_o                  ( pop_o ),
        .push_o                 ( push_o ),
        .a_sel_o                        ( a_sel_o ),
        .b_sel_o                        ( b_sel_o ),
        .imda_o                 ( imda_o ),
        .imad_o                 ( imad ),
        .sgn_o                  ( sgn_o ),
        .ext_o                  ( ext_o ),
        .lg_o                           ( lg_o ),
        .add_o                  ( add_o ),
        .sub_o                  ( sub_o ),
        .mul_o                  ( mul_o ),
        .shl_o                  ( shl_o ),
        .cpy_o                  ( cpy_o ),
        .dm_o                           ( dm_o ),
        .rtn_o                  ( rtn_o ),
        .rd_o                           ( rd_o ),
        .wr_o                           ( wr_o )
        );
 
 
        // pc generation & storage
        pc_ring
        #(
        .THREADS                        ( THREADS ),
        .THRD_W                 ( THRD_W ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .IM_ADDR_W              ( IM_ADDR_W ),
        .CLR_BASE               ( CLR_BASE ),
        .CLR_SPAN               ( CLR_SPAN ),
        .INTR_BASE              ( INTR_BASE ),
        .INTR_SPAN              ( INTR_SPAN )
        )
        pc_ring
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .thrd_0_i               ( thrd_0_o ),
        .thrd_3_i               ( thrd_3_o ),
        .clr_i                  ( pc_clr ),
        .lit_i                  ( lit ),
        .jmp_i                  ( jmp ),
        .gto_i                  ( gto ),
        .intr_i                 ( intr ),
        .imad_i                 ( imad ),
        .tst_2_i                        ( tst_2 ),
        .b_lo_i                 ( b_lo_i ),
        .im_addr_i              ( im_addr_o ),
        .pc_0_o                 (  ),
        .pc_1_o                 ( pc_1_o ),
        .pc_2_o                 (  ),
        .pc_3_o                 ( pc_3_o ),
        .pc_4_o                 ( pc_4_o ),
        .pc_5_o                 (  ),
        .pc_6_o                 (  ),
        .pc_7_o                 (  )
        );
 
 
endmodule

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[/] [hive/] [trunk/] [v01.09/] [control_ring.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : control_ring.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Processor control path.`
10
11			`Instantiates:`
12			`- (1x) thread_ring.v`
13			`- (2x) event_ctrl.v`
14			`- (1x) cond_test.v`
15			`- (1x) op_decode.v`
16			`- (1x) pc_ring.v`
17
18			`Notes:`
19			`- 8 stage data pipeline consisting of several storage rings.`
20
21			`--------------------------------------------------------------------------------`
22			`*/`
23
24			`module control_ring`
25			`#(`
26			`parameter integer DATA_W = 32, // data width`
27			`parameter integer ADDR_W = 16, // address width`
28			`parameter integer THREADS = 8, // threads`
29			`parameter integer THRD_W = 3, // thread width`
30			`parameter integer STACKS = 4, // number of stacks`
31			`parameter integer STK_W = 2, // stack selector width`
32			`parameter integer IM_DATA_W = 8, // immediate data width`
33			`parameter integer IM_ADDR_W = 6, // immediate data width`
34			`parameter integer OP_CODE_W = 16, // opcode width`
35			`parameter integer LG_W = 2, // logical operation width`
36			`parameter [ADDR_W-1:0] CLR_BASE = 'h0, // clear address base (concat)`
37			`parameter integer CLR_SPAN = 0, // clear address span (2^n)`
38			`parameter [ADDR_W-1:0] INTR_BASE = 'h8, // interrupt address base (concat)`
39			`parameter integer INTR_SPAN = 0 // interrupt address span (2^n)`
40			`)`
41			`(`
42			`// clocks & resets`
43			`input wire clk_i, // clock`
44			`input wire rst_i, // async. reset, active high`
45			`// control I/O`
46			`input wire [THREADS-1:0] clr_req_i, // clear request, active high`
47			`output wire [THREADS-1:0] clr_ack_o, // clear ack, active high until serviced`
48			`input wire [THREADS-1:0] intr_en_i, // interrupt enable, active high`
49			`input wire [THREADS-1:0] intr_req_i, // interrupt request, active high`
50			`output wire [THREADS-1:0] intr_ack_o, // interrupt ack, active high until serviced`
51			`input wire [OP_CODE_W-1:0] op_code_i, // opcode`
52			`output wire op_code_er_o, // 1=illegal op code encountered`
53			`// ALU I/O`
54			`input wire [DATA_W/2-1:0] b_lo_i, // b_lo`
55			`output wire [IM_DATA_W-1:0] im_data_o, // immediate data`
56			`output wire [STK_W-1:0] a_sel_o, // stack selector`
57			`output wire [STK_W-1:0] b_sel_o, // stack selector`
58			`output wire imda_o, // 1=immediate data`
59			`output wire sgn_o, // 1=signed`
60			`output wire ext_o, // 1=extended`
61			`output wire [LG_W-1:0] lg_o, // see decode in notes`
62			`output wire add_o, // 1=add`
63			`output wire sub_o, // 1=subtract`
64			`output wire mul_o, // 1=multiply`
65			`output wire shl_o, // 1=shift left`
66			`output wire cpy_o, // 1=copy b`
67			`output wire dm_o, // 1=data mem`
68			`output wire rtn_o, // 1=return pc`
69			`output wire rd_o, // 1=read`
70			`output wire wr_o, // 1=write`
71			`// stack I/O`
72			`output wire stk_clr_o, // stacks clear`
73			`output wire [STACKS-1:0] pop_o, // stacks pop`
74			`output wire [STACKS-1:0] push_o, // stacks push`
75			`// flags`
76			`input wire nez_i, // a != 0`
77			`input wire ne_i, // a != b`
78			`input wire ltz_i, // a < 0`
79			`input wire lt_i, // a < b`
80			`// threads`
81			`output wire [THRD_W-1:0] thrd_0_o,`
82			`output wire [THRD_W-1:0] thrd_2_o,`
83			`output wire [THRD_W-1:0] thrd_3_o,`
84			`output wire [THRD_W-1:0] thrd_6_o,`
85			`// addresses`
86			`output wire [IM_ADDR_W-1:0] im_addr_o, // immediate address (offset)`
87			`output wire [ADDR_W-1:0] pc_1_o,`
88			`output wire [ADDR_W-1:0] pc_3_o,`
89			`output wire [ADDR_W-1:0] pc_4_o`
90			`);`
91
92
93
94			`/*`
95			`----------------------`
96			`-- internal signals --`
97			`----------------------`
98			`*/`
99			`wire pc_clr, lit, jmp, gto, intr, imad, tst_2;`
100			`wire stk_clr;`
101			`wire [STACKS-1:0] pop, push;`
102			`wire tst_eq, tst_lt, tst_gt, tst_ab;`
103			`wire thrd_clr, thrd_intr;`
104			`wire [THRD_W-1:0] thrd_5;`
105
106
107
108			`/*`
109			`================`
110			`== code start ==`
111			`================`
112			`*/`
113
114
115			`// establish threads`
116			`thread_ring`
117			`#(`
118			`.THRD_W ( THRD_W )`
119			`)`
120			`thread_ring`
121			`(`
122			`.clk_i ( clk_i ),`
123			`.rst_i ( rst_i ),`
124			`.thrd_0_o ( thrd_0_o ),`
125			`.thrd_1_o ( ),`
126			`.thrd_2_o ( thrd_2_o ),`
127			`.thrd_3_o ( thrd_3_o ),`
128			`.thrd_4_o ( ),`
129			`.thrd_5_o ( thrd_5 ),`
130			`.thrd_6_o ( thrd_6_o ),`
131			`.thrd_7_o ( )`
132			`);`
133
134
135			`// handle external thread clear requests`
136			`event_ctrl`
137			`#(`
138			`.REGS_REQ ( 0 ), // don't resync`
139			`.EDGE_REQ ( 1 ), // edge sensitive`
140			`.RESET_VAL ( { THREADS{ 1'b1 } } ), // clear threads @ power-up`
141			`.THREADS ( THREADS ),`
142			`.THRD_W ( THRD_W )`
143			`)`
144			`clr_event_ctrl`
145			`(`
146			`.clk_i ( clk_i ),`
147			`.rst_i ( rst_i ),`
148			`.thrd_i ( thrd_5 ),`
149			`.en_i ( { THREADS{ 1'b1 } } ), // always enable`
150			`.req_i ( clr_req_i ),`
151			`.ack_o ( clr_ack_o ),`
152			`.event_o ( thrd_clr )`
153			`);`
154
155
156			`// handle external thread interrupt requests`
157			`event_ctrl`
158			`#(`
159			`.REGS_REQ ( 2 ), // resync`
160			`.EDGE_REQ ( 1 ), // edge sensitive`
161			`.RESET_VAL ( 0 ),`
162			`.THREADS ( THREADS ),`
163			`.THRD_W ( THRD_W )`
164			`)`
165			`intr_event_ctrl`
166			`(`
167			`.clk_i ( clk_i ),`
168			`.rst_i ( rst_i ),`
169			`.thrd_i ( thrd_5 ),`
170			`.en_i ( intr_en_i ),`
171			`.req_i ( intr_req_i ),`
172			`.ack_o ( intr_ack_o ),`
173			`.event_o ( thrd_intr )`
174			`);`
175
176
177			`// conditional jump etc. testing`
178			`cond_test`
179			`#(`
180			`.REGS_TST ( 2 ),`
181			`.REGS_OUT ( 0 )`
182			`)`
183			`cond_test`
184			`(`
185			`.clk_i ( clk_i ),`
186			`.rst_i ( rst_i ),`
187			`.nez_i ( nez_i ),`
188			`.ne_i ( ne_i ),`
189			`.ltz_i ( ltz_i ),`
190			`.lt_i ( lt_i ),`
191			`.tst_eq_i ( tst_eq ),`
192			`.tst_lt_i ( tst_lt ),`
193			`.tst_gt_i ( tst_gt ),`
194			`.tst_ab_i ( tst_ab ),`
195			`.tst_o ( tst_2 )`
196			`);`
197
198
199			`// op_code decoding`
200			`op_decode`
201			`#(`
202			`.REGS_IN ( 0 ),`
203			`.REGS_OUT ( 1 ),`
204			`.STACKS ( STACKS ),`
205			`.STK_W ( STK_W ),`
206			`.DATA_W ( DATA_W ),`
207			`.IM_DATA_W ( IM_DATA_W ),`
208			`.IM_ADDR_W ( IM_ADDR_W ),`
209			`.OP_CODE_W ( OP_CODE_W ),`
210			`.LG_W ( LG_W )`
211			`)`
212			`op_decode`
213			`(`
214			`.clk_i ( clk_i ),`
215			`.rst_i ( rst_i ),`
216			`.thrd_clr_i ( thrd_clr ),`
217			`.thrd_intr_i ( thrd_intr ),`
218			`.op_code_i ( op_code_i ),`
219			`.op_code_er_o ( op_code_er_o ),`
220			`.im_data_o ( im_data_o ),`
221			`.im_addr_o ( im_addr_o ),`
222			`.pc_clr_o ( pc_clr ),`
223			`.lit_o ( lit ),`
224			`.jmp_o ( jmp ),`
225			`.gto_o ( gto ),`
226			`.intr_o ( intr ),`
227			`.tst_eq_o ( tst_eq ),`
228			`.tst_lt_o ( tst_lt ),`
229			`.tst_gt_o ( tst_gt ),`
230			`.tst_ab_o ( tst_ab ),`
231			`.stk_clr_o ( stk_clr_o ),`
232			`.pop_o ( pop_o ),`
233			`.push_o ( push_o ),`
234			`.a_sel_o ( a_sel_o ),`
235			`.b_sel_o ( b_sel_o ),`
236			`.imda_o ( imda_o ),`
237			`.imad_o ( imad ),`
238			`.sgn_o ( sgn_o ),`
239			`.ext_o ( ext_o ),`
240			`.lg_o ( lg_o ),`
241			`.add_o ( add_o ),`
242			`.sub_o ( sub_o ),`
243			`.mul_o ( mul_o ),`
244			`.shl_o ( shl_o ),`
245			`.cpy_o ( cpy_o ),`
246			`.dm_o ( dm_o ),`
247			`.rtn_o ( rtn_o ),`
248			`.rd_o ( rd_o ),`
249			`.wr_o ( wr_o )`
250			`);`
251
252
253			`// pc generation & storage`
254			`pc_ring`
255			`#(`
256			`.THREADS ( THREADS ),`
257			`.THRD_W ( THRD_W ),`
258			`.DATA_W ( DATA_W ),`
259			`.ADDR_W ( ADDR_W ),`
260			`.IM_ADDR_W ( IM_ADDR_W ),`
261			`.CLR_BASE ( CLR_BASE ),`
262			`.CLR_SPAN ( CLR_SPAN ),`
263			`.INTR_BASE ( INTR_BASE ),`
264			`.INTR_SPAN ( INTR_SPAN )`
265			`)`
266			`pc_ring`
267			`(`
268			`.clk_i ( clk_i ),`
269			`.rst_i ( rst_i ),`
270			`.thrd_0_i ( thrd_0_o ),`
271			`.thrd_3_i ( thrd_3_o ),`
272			`.clr_i ( pc_clr ),`
273			`.lit_i ( lit ),`
274			`.jmp_i ( jmp ),`
275			`.gto_i ( gto ),`
276			`.intr_i ( intr ),`
277			`.imad_i ( imad ),`
278			`.tst_2_i ( tst_2 ),`
279			`.b_lo_i ( b_lo_i ),`
280			`.im_addr_i ( im_addr_o ),`
281			`.pc_0_o ( ),`
282			`.pc_1_o ( pc_1_o ),`
283			`.pc_2_o ( ),`
284			`.pc_3_o ( pc_3_o ),`
285			`.pc_4_o ( pc_4_o ),`
286			`.pc_5_o ( ),`
287			`.pc_6_o ( ),`
288			`.pc_7_o ( )`
289			`);`
290
291
292			`endmodule`