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ericw |
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Module : pc_ring.v
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--------------------------------------------------------------------------------
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Function:
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- Processor PC storage ring.
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Instantiates:
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- (2x) vector_sr.v
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Notes:
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- 8 stages.
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- Loop feedback, so PC interstage pipe registering forms a storage ring.
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--------------------------------------------------------------------------------
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*/
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module pc_ring
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#(
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parameter integer THREADS = 8, // threads
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parameter integer THRD_W = 2, // thread width
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parameter integer DATA_W = 32, // data width
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parameter integer ADDR_W = 16, // address width
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parameter integer IM_ADDR_W = 5, // immediate data width
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parameter [ADDR_W-1:0] CLR_BASE = 'h8, // clear address base (concat)
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parameter integer CLR_SPAN = 0, // clear address span (2^n)
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parameter [ADDR_W-1:0] INTR_BASE = 'h0, // interrupt address base (concat)
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parameter integer INTR_SPAN = 0 // interrupt address span (2^n)
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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// control I/O
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input wire [THRD_W-1:0] thrd_0_i, // thread
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input wire [THRD_W-1:0] thrd_3_i, // thread
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input wire clr_i, // 1=pc clear
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input wire lit_i, // 1 : pc=pc++ for lit
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input wire jmp_i, // 1 : pc=pc+B for jump (cond)
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input wire gto_i, // 1 : pc=B for goto / gosub (cond)
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input wire intr_i, // 1 : pc=int
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input wire imad_i, // 1=immediate address
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input wire tst_2_i, // 1=true; 0=false
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// data I/O
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input wire [DATA_W/2-1:0] b_lo_i, // b_lo
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// address I/O
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input wire [IM_ADDR_W-1:0] im_addr_i, // immediate address (offset)
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output wire [ADDR_W-1:0] pc_0_o,
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output wire [ADDR_W-1:0] pc_1_o,
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output wire [ADDR_W-1:0] pc_2_o,
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output wire [ADDR_W-1:0] pc_3_o,
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output wire [ADDR_W-1:0] pc_4_o,
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output wire [ADDR_W-1:0] pc_5_o,
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output wire [ADDR_W-1:0] pc_6_o,
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output wire [ADDR_W-1:0] pc_7_o
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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reg [ADDR_W-1:0] pc[0:THREADS-1];
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//
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wire [ADDR_W-1:0] clr_addr, intr_addr;
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wire intr_2, gto_2, jmp_2, lit_2;
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wire intr_3, gto_3;
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wire tst_3;
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wire signed [DATA_W/2-1:0] b_im, b_im_2, b_im_3;
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reg [ADDR_W-1:0] pc_1_mux, pc_3_mux, pc_4_mux;
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/*
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================
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== code start ==
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================
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*/
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// form the clear address
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assign clr_addr[ADDR_W-1:THRD_W+CLR_SPAN] = CLR_BASE[ADDR_W-1:THRD_W+CLR_SPAN];
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assign clr_addr[THRD_W+CLR_SPAN-1:0] = thrd_0_i << CLR_SPAN;
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// mux for clear, next
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always @ ( * ) begin
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casex ( { clr_i, intr_i } )
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'b00 : pc_1_mux <= pc[0] + 1'b1; // inc for next
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'b01 : pc_1_mux <= pc[0]; // no change for int
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'b1x : pc_1_mux <= clr_addr; // clear
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endcase
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end
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// decode immediate offset
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assign b_im = ( imad_i ) ? $signed( im_addr_i ) : $signed( b_lo_i );
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// in to 2 regs
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vector_sr
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#(
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.REGS ( 2 ),
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.DATA_W ( DATA_W/2+4 ),
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.RESET_VAL ( 0 )
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)
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regs_in_2
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.data_i ( { b_im, intr_i, gto_i, jmp_i, lit_i } ),
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.data_o ( { b_im_2, intr_2, gto_2, jmp_2, lit_2 } )
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);
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// mux for lit, jump
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always @ ( * ) begin
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casex ( { jmp_2, lit_2 } )
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3'b00 : pc_3_mux <= pc[2]; // no change
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3'b01 : pc_3_mux <= pc[2] + 1'b1; // inc for lit
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3'b1x : pc_3_mux <= ( tst_2_i ) ? pc[2] + b_im_2 : pc[2]; // offset for jump
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endcase
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end
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// 2 to 3 regs
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vector_sr
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#(
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.REGS ( 1 ),
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.DATA_W ( DATA_W/2+3 ),
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.RESET_VAL ( 0 )
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)
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regs_2_3
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.data_i ( { b_im_2, intr_2, gto_2, tst_2_i } ),
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.data_o ( { b_im_3, intr_3, gto_3, tst_3 } )
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);
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// form the interrupt address
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assign intr_addr[ADDR_W-1:THRD_W+INTR_SPAN] = INTR_BASE[ADDR_W-1:THRD_W+INTR_SPAN];
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assign intr_addr[THRD_W+INTR_SPAN-1:0] = thrd_3_i << INTR_SPAN;
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// mux for goto, gosub, interrupt
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always @ ( * ) begin
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casex ( { intr_3, gto_3 } )
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'b00 : pc_4_mux <= pc[3]; // no change
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'b01 : pc_4_mux <= ( tst_3 ) ? b_im_3 : pc[3]; // absolute goto / gosub
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'b1x : pc_4_mux <= intr_addr; // interrupt address
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endcase
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end
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// pc storage ring
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integer j;
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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for ( j = 0; j < THREADS; j = j + 1 ) begin
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pc[j] <= 'b0;
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end
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end else begin
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for ( j = 0; j < THREADS; j = j + 1 ) begin
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if ( j == 0 ) pc[j] <= pc[THREADS-1]; // wrap around
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else if ( j == 1 ) pc[j] <= pc_1_mux;
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else if ( j == 3 ) pc[j] <= pc_3_mux;
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else if ( j == 4 ) pc[j] <= pc_4_mux;
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else pc[j] <= pc[j-1];
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end
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end
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end
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// output pc
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assign pc_0_o = pc[0];
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assign pc_1_o = pc[1];
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assign pc_2_o = pc[2];
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assign pc_3_o = pc[3];
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assign pc_4_o = pc[4];
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assign pc_5_o = pc[5];
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assign pc_6_o = pc[6];
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assign pc_7_o = pc[7];
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endmodule
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