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[/] [hive/] [trunk/] [v01.10/] [README.txt] - Blame information for rev 8
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ericw |
* Hive soft processor core readme file *
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- All *.v verilog and include *.h files are in a single directory,
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where "core.v" is the top level entry.
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- There are several boot code files in the "boot_code" directory,
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to use one, bring it into the main directory and rename it
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"boot_code.h".
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- There is also an "unused" directory which contains files that aren't
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currently part of the project but may be of interest.
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- There is a "core.qpf" project file for Altera Quartus II9.1sp2 Web Edition.
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With this tool you can compile to a target, and with the file "core.vwf" you
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can simulate. I recommend functional simulation when fiddling around
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because the compile is much faster.
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- There is also a "core.sdc" file which sets the target top speed to
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200 MHz in Quartus, and "core.qsf" which is a project settings file.
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- Don't forget to assign pins when doing a real project!
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