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/*
--------------------------------------------------------------------------------
 
Module : alu_top.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor ALU top level.
 
Instantiates:
- (2x) vector_sr.v
- (1x) alu_logical.v
  - (4x) vector_sr.v
- (1x) alu_add_sub.v
  - (4x) vector_sr.v
- (1x) alu_mult_shift.v
  - (3x) vector_sr.v
  - (1x) alu_multiply.v
    - (1x) vector_sr.v (debug mode only)
- (1x) alu_mux.v
  - (4x) vector_sr.v
 
Notes:
- I/O optionally registered.
- 5 stage pipeline w/ 4 mid registers (not counting I/O registering).
 
--------------------------------------------------------------------------------
*/
 
module alu_top
        #(
        parameter       integer                                                 REGS_IN                 = 1,            // register option for control and a & b inputs
        parameter       integer                                                 REGS_OUT                        = 1,            // register option for outputs
        parameter       integer                                                 REGS_FLG                        = 1,            // register option for flag outputs
        parameter       integer                                                 DATA_W                  = 32,           // data width
        parameter       integer                                                 ADDR_W                  = 16,           // address width
        parameter       integer                                                 LG_W                            = 2             // operation width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire                                                            sgn_i,                                          // 1=signed
        input                   wire                                                            ext_i,                                          // 1=extended result
        input                   wire    [LG_W-1:0]                               lg_i,                                                   // see decode in notes above
        input                   wire                                                            add_i,                                          // 1=add
        input                   wire                                                            sub_i,                                          // 1=subtract
        input                   wire                                                            mul_i,                                          // 1=multiply
        input                   wire                                                            shl_i,                                          // 1=shift left
        input                   wire                                                            cpy_i,                                          // 1=copy b
        input                   wire                                                            dm_i,                                                   // 1=data mem
        input                   wire                                                            rtn_i,                                          // 1=return pc
        // data I/O
        input                   wire    [DATA_W-1:0]                     a_i,                                                    // operand
        input                   wire    [DATA_W-1:0]                     b_i,                                                    // operand
        input                   wire    [DATA_W/2-1:0]                   dm_data_i,                                      // dmem read data
        input                   wire    [ADDR_W-1:0]                     pc_3_i,                                         // program counter
        output          wire    [DATA_W-1:0]                     result_o,                                       // result
        // flags
        output          wire                                                            nez_o,                                          //      a != 0
        output          wire                                                            ne_o,                                                   //      a != b
        output          wire                                                            ltz_o,                                          //      a < 0
        output          wire                                                            lt_o                                                    //      a < b
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                                                                            rtn, dm, cpy, shl, mul, sub, add, ext, sgn;
        wire                                    [LG_W-1:0]                               lg;
        wire                                    [DATA_W-1:0]                     a, b;
        wire                                    [DATA_W-1:0]                     res_lg, res_as, res_mid, res_ms;
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // optional input regs
        vector_sr
        #(
        .REGS                   ( REGS_IN ),
        .DATA_W         ( DATA_W+DATA_W+7+LG_W+2 ),
        .RESET_VAL      ( 0 )
        )
        in_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { a_i, b_i, rtn_i, dm_i, cpy_i, shl_i, mul_i, sub_i, add_i, lg_i, ext_i, sgn_i } ),
        .data_o         ( { a,   b,   rtn,   dm,   cpy,   shl,   mul,   sub,   add,   lg,   ext,   sgn } )
        );
 
 
        // logical unit
        alu_logical
        #(
        .REGS_IN                        ( 0 ),
        .REGS_MID               ( 1 ),
        .REGS_OUT               ( 0 ),
        .REGS_FLG               ( REGS_FLG ),
        .DATA_W                 ( DATA_W ),
        .LG_W                           ( LG_W )
        )
        alu_logical
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .ext_i                  ( ext ),
        .lg_i                           ( lg ),
        .a_i                            ( a ),
        .b_i                            ( b ),
        .result_o               ( res_lg ),
        .nez_o                  ( nez_o ),
        .ne_o                           ( ne_o )
        );
 
 
        // add & subtract unit
        alu_add_sub
        #(
        .REGS_IN                        ( 0 ),
        .REGS_MID               ( 1 ),
        .REGS_OUT               ( 0 ),
        .REGS_FLG               ( REGS_FLG ),
        .DATA_W                 ( DATA_W )
        )
        alu_add_sub
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .sgn_i                  ( sgn ),
        .ext_i                  ( ext ),
        .sub_i                  ( sub ),
        .a_i                            ( a ),
        .b_i                            ( b ),
        .result_o               ( res_as ),
        .ltz_o                  ( ltz_o ),
        .lt_o                           ( lt_o )
        );
 
 
        // multiply & shift unit
        alu_mult_shift
        #(
        .REGS_IN                        ( 0 ),
        .REGS_OUT               ( 0 ),
        .DATA_W                 ( DATA_W )
        )
        alu_mult_shift
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .sgn_i                  ( sgn ),
        .ext_i                  ( ext ),
        .shl_i                  ( shl ),
        .cpy_i                  ( cpy ),
        .a_i                            ( a ),
        .b_i                            ( b ),
        .result_o               ( res_ms )
        );
 
 
        // multiplexer
        alu_mux
        #(
        .REGS_IN_A              ( 1 ),
        .REGS_A_B               ( 1 ),
        .REGS_B_C               ( 1 ),
        .REGS_C_D               ( 1 ),
        .REGS_D_OUT             ( REGS_OUT ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W )
        )
        alu_mux
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .sgn_i                  ( sgn ),
        .ext_i                  ( ext ),
        .as_i                           ( sub | add ),
        .dm_i                           ( dm ),
        .rtn_i                  ( rtn ),
        .ms_i                           ( cpy | shl | mul ),
        .a_lo_i                 ( a[DATA_W/2-1:0] ),
        .res_ms_i               ( res_ms ),
        .res_lg_i               ( res_lg ),
        .res_as_i               ( res_as ),
        .dm_data_i              ( dm_data_i ),
        .pc_i                           ( pc_3_i ),
        .result_o               ( result_o )
        );
 
 
endmodule

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[/] [hive/] [trunk/] [v01.10/] [alu_top.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : alu_top.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Processor ALU top level.`
10
11			`Instantiates:`
12			`- (2x) vector_sr.v`
13			`- (1x) alu_logical.v`
14			`- (4x) vector_sr.v`
15			`- (1x) alu_add_sub.v`
16			`- (4x) vector_sr.v`
17			`- (1x) alu_mult_shift.v`
18			`- (3x) vector_sr.v`
19			`- (1x) alu_multiply.v`
20			`- (1x) vector_sr.v (debug mode only)`
21			`- (1x) alu_mux.v`
22			`- (4x) vector_sr.v`
23
24			`Notes:`
25			`- I/O optionally registered.`
26			`- 5 stage pipeline w/ 4 mid registers (not counting I/O registering).`
27
28			`--------------------------------------------------------------------------------`
29			`*/`
30
31			`module alu_top`
32			`#(`
33			`parameter integer REGS_IN = 1, // register option for control and a & b inputs`
34			`parameter integer REGS_OUT = 1, // register option for outputs`
35			`parameter integer REGS_FLG = 1, // register option for flag outputs`
36			`parameter integer DATA_W = 32, // data width`
37			`parameter integer ADDR_W = 16, // address width`
38			`parameter integer LG_W = 2 // operation width`
39			`)`
40			`(`
41			`// clocks & resets`
42			`input wire clk_i, // clock`
43			`input wire rst_i, // async. reset, active high`
44			`// control I/O`
45			`input wire sgn_i, // 1=signed`
46			`input wire ext_i, // 1=extended result`
47			`input wire [LG_W-1:0] lg_i, // see decode in notes above`
48			`input wire add_i, // 1=add`
49			`input wire sub_i, // 1=subtract`
50			`input wire mul_i, // 1=multiply`
51			`input wire shl_i, // 1=shift left`
52			`input wire cpy_i, // 1=copy b`
53			`input wire dm_i, // 1=data mem`
54			`input wire rtn_i, // 1=return pc`
55			`// data I/O`
56			`input wire [DATA_W-1:0] a_i, // operand`
57			`input wire [DATA_W-1:0] b_i, // operand`
58			`input wire [DATA_W/2-1:0] dm_data_i, // dmem read data`
59			`input wire [ADDR_W-1:0] pc_3_i, // program counter`
60			`output wire [DATA_W-1:0] result_o, // result`
61			`// flags`
62			`output wire nez_o, // a != 0`
63			`output wire ne_o, // a != b`
64			`output wire ltz_o, // a < 0`
65			`output wire lt_o // a < b`
66			`);`
67
68
69			`/*`
70			`----------------------`
71			`-- internal signals --`
72			`----------------------`
73			`*/`
74			`wire rtn, dm, cpy, shl, mul, sub, add, ext, sgn;`
75			`wire [LG_W-1:0] lg;`
76			`wire [DATA_W-1:0] a, b;`
77			`wire [DATA_W-1:0] res_lg, res_as, res_mid, res_ms;`
78
79
80			`/*`
81			`================`
82			`== code start ==`
83			`================`
84			`*/`
85
86
87			`// optional input regs`
88			`vector_sr`
89			`#(`
90			`.REGS ( REGS_IN ),`
91			`.DATA_W ( DATA_W+DATA_W+7+LG_W+2 ),`
92			`.RESET_VAL ( 0 )`
93			`)`
94			`in_regs`
95			`(`
96			`.clk_i ( clk_i ),`
97			`.rst_i ( rst_i ),`
98			`.data_i ( { a_i, b_i, rtn_i, dm_i, cpy_i, shl_i, mul_i, sub_i, add_i, lg_i, ext_i, sgn_i } ),`
99			`.data_o ( { a, b, rtn, dm, cpy, shl, mul, sub, add, lg, ext, sgn } )`
100			`);`
101
102
103			`// logical unit`
104			`alu_logical`
105			`#(`
106			`.REGS_IN ( 0 ),`
107			`.REGS_MID ( 1 ),`
108			`.REGS_OUT ( 0 ),`
109			`.REGS_FLG ( REGS_FLG ),`
110			`.DATA_W ( DATA_W ),`
111			`.LG_W ( LG_W )`
112			`)`
113			`alu_logical`
114			`(`
115			`.clk_i ( clk_i ),`
116			`.rst_i ( rst_i ),`
117			`.ext_i ( ext ),`
118			`.lg_i ( lg ),`
119			`.a_i ( a ),`
120			`.b_i ( b ),`
121			`.result_o ( res_lg ),`
122			`.nez_o ( nez_o ),`
123			`.ne_o ( ne_o )`
124			`);`
125
126
127			`// add & subtract unit`
128			`alu_add_sub`
129			`#(`
130			`.REGS_IN ( 0 ),`
131			`.REGS_MID ( 1 ),`
132			`.REGS_OUT ( 0 ),`
133			`.REGS_FLG ( REGS_FLG ),`
134			`.DATA_W ( DATA_W )`
135			`)`
136			`alu_add_sub`
137			`(`
138			`.clk_i ( clk_i ),`
139			`.rst_i ( rst_i ),`
140			`.sgn_i ( sgn ),`
141			`.ext_i ( ext ),`
142			`.sub_i ( sub ),`
143			`.a_i ( a ),`
144			`.b_i ( b ),`
145			`.result_o ( res_as ),`
146			`.ltz_o ( ltz_o ),`
147			`.lt_o ( lt_o )`
148			`);`
149
150
151			`// multiply & shift unit`
152			`alu_mult_shift`
153			`#(`
154			`.REGS_IN ( 0 ),`
155			`.REGS_OUT ( 0 ),`
156			`.DATA_W ( DATA_W )`
157			`)`
158			`alu_mult_shift`
159			`(`
160			`.clk_i ( clk_i ),`
161			`.rst_i ( rst_i ),`
162			`.sgn_i ( sgn ),`
163			`.ext_i ( ext ),`
164			`.shl_i ( shl ),`
165			`.cpy_i ( cpy ),`
166			`.a_i ( a ),`
167			`.b_i ( b ),`
168			`.result_o ( res_ms )`
169			`);`
170
171
172			`// multiplexer`
173			`alu_mux`
174			`#(`
175			`.REGS_IN_A ( 1 ),`
176			`.REGS_A_B ( 1 ),`
177			`.REGS_B_C ( 1 ),`
178			`.REGS_C_D ( 1 ),`
179			`.REGS_D_OUT ( REGS_OUT ),`
180			`.DATA_W ( DATA_W ),`
181			`.ADDR_W ( ADDR_W )`
182			`)`
183			`alu_mux`
184			`(`
185			`.clk_i ( clk_i ),`
186			`.rst_i ( rst_i ),`
187			`.sgn_i ( sgn ),`
188			`.ext_i ( ext ),`
189			`.as_i ( sub \| add ),`
190			`.dm_i ( dm ),`
191			`.rtn_i ( rtn ),`
192			`.ms_i ( cpy \| shl \| mul ),`
193			`.a_lo_i ( a[DATA_W/2-1:0] ),`
194			`.res_ms_i ( res_ms ),`
195			`.res_lg_i ( res_lg ),`
196			`.res_as_i ( res_as ),`
197			`.dm_data_i ( dm_data_i ),`
198			`.pc_i ( pc_3_i ),`
199			`.result_o ( result_o )`
200			`);`
201
202
203			`endmodule`