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ericw |
/*
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--------------------------------------------------------------------------------
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Module : boot_code.h
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--------------------------------------------------------------------------------
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Function:
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- Boot code for a processor core.
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Instantiates:
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- Nothing.
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Notes:
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- For testing (@ core.v):
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CLR_BASE = 'h0;
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CLR_SPAN = 2; // gives 4 instructions
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INTR_BASE = 'h20; // 'd32
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INTR_SPAN = 2; // gives 4 instructions
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--------------------------------------------------------------------------------
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*/
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/*
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-------------------------
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-- external parameters --
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-------------------------
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*/
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`include "op_encode.h"
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`include "reg_set_addr.h"
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/*
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------------------------------------------------------------
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-- defines that make programming code more human readable --
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------------------------------------------------------------
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*/
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`define s0 2'd0
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`define s1 2'd1
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`define s2 2'd2
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`define s3 2'd3
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`define _ 1'b0
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`define P 1'b1
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//
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`define op_rd_i op_rd_i[9:4]
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`define op_rd_ix op_rd_ix[9:4]
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//
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`define op_jmp_iez op_jmp_iez[9:5]
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`define op_jmp_ilz op_jmp_ilz[9:5]
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`define op_jmp_ilez op_jmp_ilez[9:5]
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`define op_jmp_igz op_jmp_igz[9:5]
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`define op_jmp_igez op_jmp_igez[9:5]
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`define op_jmp_iglz op_jmp_iglz[9:5]
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`define op_jmp_i op_jmp_i[9:5]
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//
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`define op_wr_i op_wr_i[9:4]
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`define op_wr_ix op_wr_ix[9:4]
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//
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`define op_jmp_ie op_jmp_ie[9:5]
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`define op_jmp_il op_jmp_il[9:5]
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`define op_jmp_ile op_jmp_ile[9:5]
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`define op_jmp_iug op_jmp_iug[9:5]
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`define op_jmp_iuge op_jmp_iuge[9:5]
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`define op_jmp_igl op_jmp_igl[9:5]
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//
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`define op_byt_i op_byt_i[9:8]
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//
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`define op_shl_i op_shl_i[9:6]
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`define op_shl_iu op_shl_iu[9:6]
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`define op_add_i op_add_i[9:6]
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/*
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----------------------------------------
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-- initialize: fill with default data --
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----------------------------------------
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*/
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integer i;
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initial begin
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/* // fill with nop (some compilers need this)
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for ( i = 0; i < CAPACITY; i = i+1 ) begin
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ram[i] = { op_nop, `_, `_, `s0, `s0 };
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end
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*/
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/*
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---------------
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-- boot code --
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---------------
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*/
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/*
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------------
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-- TEST 0 --
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------------
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*/
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// Log base 2
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// Thread 0 : Get input 32 bit GPIO, calculate log2, output 32 bit GPIO.
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// Other threads : do nothing, loop forever
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///////////////
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// clr space //
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///////////////
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i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
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i=i+1; ram[i] = 16'h040 ; // addr
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i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // goto, pop s1 (addr)
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//
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i='h4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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////////////////
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// intr space //
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////////////////
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///////////////////////
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// code & data space //
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///////////////////////
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// read 32 bit GPIO data to s0
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i='h40; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
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i=i+1; ram[i] = 16'h050 ; // addr
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i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
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// write s0 data to 32 bit GPIO
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i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
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i=i+1; ram[i] = 16'h058 ; // addr
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i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
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// do log2 of s0
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i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
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i=i+1; ram[i] = 16'h060 ; // addr
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i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
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// write s0 data to 32 bit GPIO
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i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
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i=i+1; ram[i] = 16'h058 ; // addr
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i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
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// loop forever
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i=i+1; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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// sub : read 32 bit GPIO => s0, return to (s3)
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i='h50; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
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i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
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i=i+1; ram[i] = { `op_rd_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // read (s1+offset) => s0
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i=i+1; ram[i] = { `op_rd_ix, IO_HI_ADDR, `P, `P, `s1, `s0 }; // read (s1+offset) => s0, pop s1 & s0
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i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
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// sub : write s0 => 32 bit GPIO, return to (s3)
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i='h58; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
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i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
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i=i+1; ram[i] = { `op_wr_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // write s0 => (s1+offset)
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i=i+1; ram[i] = { `op_wr_ix, IO_HI_ADDR, `P, `_, `s1, `s0 }; // write s0 => (s1+offset), pop s1
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i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
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// sub : log2(s0)=>s0, return to (s3)
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//
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// s0 : input, normalize, square, output
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// s1 : characteristic (5 MSBs of output) and mantissa (27 LSBs of output)
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// s2 : loop index
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// s3 : subroutine return address
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//
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// input 0 is an error, return
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i='h60; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s0 }; // (s0!==0) ? skip return
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i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
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// normalize binary search
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i=i+1; ram[i] = { `op_byt_i, 8'd31, `_, `_, `s0, `s1 }; // 31=>s1, characteristic
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//
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i=i+1; ram[i] = { `op_shl_iu, -6'd16, `_, `_, `s0, `s0 }; // s0>>16=>s0
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i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
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i=i+1; ram[i] = { `op_shl_i, 6'd16, `_, `P, `s0, `s0 }; // s0<<16=>s0, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd16, `_, `P, `s0, `s1 }; // s1-16=>s1, pop s1
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//
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i=i+1; ram[i] = { `op_shl_iu, -6'd24, `_, `_, `s0, `s0 }; // s0>>24=>s0
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i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
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i=i+1; ram[i] = { `op_shl_i, 6'd8, `_, `P, `s0, `s0 }; // s0<<8=>s0, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd8, `_, `P, `s0, `s1 }; // s1-8=>s1, pop s1
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//
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i=i+1; ram[i] = { `op_shl_iu, -6'd28, `_, `_, `s0, `s0 }; // s0>>28=>s0
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i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
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i=i+1; ram[i] = { `op_shl_i, 6'd4, `_, `P, `s0, `s0 }; // s0<<4=>s0, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd4, `_, `P, `s0, `s1 }; // s1-4=>s1, pop s1
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//
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i=i+1; ram[i] = { `op_shl_iu, -6'd30, `_, `_, `s0, `s0 }; // s0>>30=>s0
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i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
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i=i+1; ram[i] = { `op_shl_i, 6'd2, `_, `P, `s0, `s0 }; // s0<<2=>s0, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s1 }; // s1-2=>s1, pop s1
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//
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i=i+1; ram[i] = { `op_jmp_ilz, 5'd2, `_, `_, `s0, `s0 }; // (s0<0) ? jump
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i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s0 }; // s0<<1=>s0, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s1 }; // s1-1=>s1, pop s1
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// loop setup
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i=i+1; ram[i] = { `op_byt_i, 8'd27, `_, `_, `s0, `s2 }; // 27=>s2
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// square loop
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s2 }; // s2--=>s2, pop s2
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i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s1 }; // s1<<1=>s1, pop s1
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i=i+1; ram[i] = { op_mul_ux, `_, `P, `s0, `s0 }; // s0*s0=>s0, pop s0
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i=i+1; ram[i] = { `op_jmp_igez, 5'd2, `_, `_, `s0, `s0 }; // (s0[31]==0) ? jump
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s1 }; // s1++=>s1, pop s1
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i=i+1; ram[i] = { `op_jmp_i, 5'd1, `_, `_, `s0, `s0 }; // skip
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i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s0 }; // s0<<1=>s0, pop s0
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i=i+1; ram[i] = { `op_jmp_igz, -5'd8, `_, `_, `s3, `s2 }; // (s2>0) ? do again
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// s1=>s0; cleanup, return
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i=i+1; ram[i] = { op_cpy, `P, `P, `s1, `s0 }; // s1=>s0, pop both
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i=i+1; ram[i] = { op_gto, `P, `P, `s3, `s2 }; // return, pop s3 & s2
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// end sub
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end
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