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ericw |
/*
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--------------------------------------------------------------------------------
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Module : boot_code.h
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--------------------------------------------------------------------------------
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Function:
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- Boot code for a processor core.
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Instantiates:
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- Nothing.
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Notes:
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- For testing (@ core.v):
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CLR_BASE = 'h0;
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CLR_SPAN = 2; // gives 4 instructions
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INTR_BASE = 'h20; // 'd32
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INTR_SPAN = 2; // gives 4 instructions
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--------------------------------------------------------------------------------
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*/
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/*
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-------------------------
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-- external parameters --
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-------------------------
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*/
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`include "op_encode.h"
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`include "reg_set_addr.h"
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/*
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------------------------------------------------------------
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-- defines that make programming code more human readable --
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------------------------------------------------------------
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*/
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`define s0 2'd0
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`define s1 2'd1
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`define s2 2'd2
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`define s3 2'd3
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`define _ 1'b0
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`define P 1'b1
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//
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`define op_rd_i op_rd_i[9:4]
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`define op_rd_ix op_rd_ix[9:4]
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//
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`define op_jmp_iez op_jmp_iez[9:5]
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`define op_jmp_ilz op_jmp_ilz[9:5]
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`define op_jmp_ilez op_jmp_ilez[9:5]
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`define op_jmp_igz op_jmp_igz[9:5]
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`define op_jmp_igez op_jmp_igez[9:5]
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`define op_jmp_iglz op_jmp_iglz[9:5]
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`define op_jmp_i op_jmp_i[9:5]
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//
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`define op_wr_i op_wr_i[9:4]
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`define op_wr_ix op_wr_ix[9:4]
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//
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`define op_jmp_ie op_jmp_ie[9:5]
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`define op_jmp_il op_jmp_il[9:5]
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`define op_jmp_ile op_jmp_ile[9:5]
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`define op_jmp_iug op_jmp_iug[9:5]
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`define op_jmp_iuge op_jmp_iuge[9:5]
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`define op_jmp_igl op_jmp_igl[9:5]
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//
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`define op_byt_i op_byt_i[9:8]
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//
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`define op_shl_i op_shl_i[9:6]
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`define op_shl_iu op_shl_iu[9:6]
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`define op_add_i op_add_i[9:6]
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/*
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----------------------------------------
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-- initialize: fill with default data --
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----------------------------------------
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*/
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integer i;
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initial begin
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/* // fill with nop (some compilers need this)
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for ( i = 0; i < CAPACITY; i = i+1 ) begin
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ram[i] = { op_nop, `_, `_, `s0, `s0 };
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end
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*/
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/*
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---------------
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-- boot code --
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---------------
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*/
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// Thread 0 : test ALU logical functions
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// Thread 1 : test ALU arithmetic functions
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// Thread 2 : test ALU shift functions
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// All other threads : loop forever
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///////////////
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// clr space //
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///////////////
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// thread 0
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i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
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i=i+1; ram[i] = 16'h100 ; // addr
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i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
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// thread 1
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i='h4; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
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i=i+1; ram[i] = 16'h200 ; // addr
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i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
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// thread 2
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i='h8; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
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i=i+1; ram[i] = 16'h300 ; // addr
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i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
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// and the rest (are here on Gilligan's Isle)
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i='hc; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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i=i+4; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
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////////////////
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// intr space //
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////////////////
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///////////////////////
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// code & data space //
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///////////////////////
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// test ALU logical functions, result in s0
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// Correct functioning is s0 = 'd12 ('hc).
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//
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// s0 : final test result
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// s1 : test value
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// s2 : test value
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// s3 : running test result, subroutine return address
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//
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// setup running test result:
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i='h100; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
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// load s1 & s2 values
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i=i+1; ram[i] = { `op_byt_i, -8'h1, `_, `_, `s1, `s1 }; // -1 => s1
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i=i+1; ram[i] = { `op_byt_i, 8'h1, `_, `_, `s2, `s2 }; // 1 => s2
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// AND_B ( &(-1)=-1; &(1)= 0 )
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i=i+1; ram[i] = { op_and_b, `_, `_, `s1, `s0 }; // &s1=>s0
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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//
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i=i+1; ram[i] = { op_and_b, `_, `_, `s2, `s0 }; // &s2=>s0
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i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// OR_B ( |(-1)=-1; |(1)=-1 )
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i=i+1; ram[i] = { op_or_b, `_, `_, `s1, `s0 }; // |s1=>s0
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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//
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i=i+1; ram[i] = { op_or_b, `_, `_, `s2, `s0 }; // |s2=>s0
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// XOR_B ( ^(-1)= 0; ^(1)=-1 )
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i=i+1; ram[i] = { op_xor_b, `_, `_, `s1, `s0 }; // ^s1=>s0
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i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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//
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i=i+1; ram[i] = { op_xor_b, `_, `_, `s2, `s0 }; // ^s2=>s0
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// clean up
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i=i+1; ram[i] = { op_pop, `P, `P, `s2, `s1 }; // pop s2 & s1
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// load s1 & s2 values
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i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
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i=i+1; ram[i] = 16'ha53c ; // lo data
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i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
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i=i+1; ram[i] = 16'h36c9 ; // hi data
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//
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i=i+1; ram[i] = { op_lit, `_, `_, `s2, `s2 }; // lit => s2
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i=i+1; ram[i] = 16'hc396 ; // lo data
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i=i+1; ram[i] = { op_lit_x, `_, `P, `s2, `s2 }; // lit => s2, pop combine
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i=i+1; ram[i] = 16'h5ca3 ; // hi data
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// AND (s/b 'h1481,8114)
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i=i+1; ram[i] = { op_and, `_, `_, `s2, `s1 }; // s1&s2=>s1
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i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
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i=i+1; ram[i] = 16'h8114 ; // lo data
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i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
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i=i+1; ram[i] = 16'h1481 ; // hi data
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// OR (s/b 'h7eeb,e7be)
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i=i+1; ram[i] = { op_or, `_, `_, `s2, `s1 }; // s1|s2=>s1
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i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
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i=i+1; ram[i] = 16'he7be ; // lo data
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i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
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i=i+1; ram[i] = 16'h7eeb ; // hi data
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// XOR (s/b 'h6a6a,66aa)
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i=i+1; ram[i] = { op_xor, `_, `_, `s2, `s1 }; // s1^s2=>s1
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i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
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i=i+1; ram[i] = 16'h66aa ; // lo data
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i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
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i=i+1; ram[i] = 16'h6a6a ; // hi data
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// NOT (s/b 'hc936,5ac3)
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i=i+1; ram[i] = { op_not, `_, `_, `s1, `s1 }; // ~s1=>s1
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i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
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i=i+1; ram[i] = 16'h5ac3 ; // lo data
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i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
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i=i+1; ram[i] = 16'hc936 ; // hi data
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i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// check for no opcode errors
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i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
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i=i+1; ram[i] = 16'h900 ; // addr
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i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
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| 227 |
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i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
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| 228 |
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i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
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| 229 |
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i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
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// check for no stack errors
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i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
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i=i+1; ram[i] = 16'h910 ; // addr
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i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
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| 234 |
|
|
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
|
| 235 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 236 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 237 |
|
|
// s3=>s0, loop forever
|
| 238 |
|
|
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
|
| 239 |
|
|
i=i+1; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
|
| 240 |
|
|
|
| 241 |
|
|
|
| 242 |
|
|
|
| 243 |
|
|
// test ALU arithmetic functions, result in s0
|
| 244 |
|
|
// Correct functioning is s0 = 'd13 ('hd).
|
| 245 |
|
|
//
|
| 246 |
|
|
// s0 : final test result
|
| 247 |
|
|
// s1 : test value
|
| 248 |
|
|
// s2 : test value
|
| 249 |
|
|
// s3 : running test result, subroutine return address
|
| 250 |
|
|
//
|
| 251 |
|
|
// setup running test result:
|
| 252 |
|
|
i='h200; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
|
| 253 |
|
|
// load s1 & s2 values
|
| 254 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
|
| 255 |
|
|
i=i+1; ram[i] = 16'h36c9 ; // hi data
|
| 256 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
|
| 257 |
|
|
i=i+1; ram[i] = 16'ha53c ; // lo data
|
| 258 |
|
|
//
|
| 259 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s2, `s2 }; // lit => s2
|
| 260 |
|
|
i=i+1; ram[i] = 16'hc396 ; // lo data
|
| 261 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s2, `s2 }; // lit => s2, pop combine
|
| 262 |
|
|
i=i+1; ram[i] = 16'h5ca3 ; // hi data
|
| 263 |
|
|
// ADD_I -32 (s/b 'ha53c,36a9)
|
| 264 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd32, `_, `_, `s1, `s1 }; // s1-32=>s1
|
| 265 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 266 |
|
|
i=i+1; ram[i] = 16'h36a9 ; // lo data
|
| 267 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 268 |
|
|
i=i+1; ram[i] = 16'ha53c ; // hi data
|
| 269 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 270 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 271 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 272 |
|
|
// ADD_I +31 (s/b 'ha53c,36e8)
|
| 273 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd31, `_, `_, `s1, `s1 }; // s1+31=>s1
|
| 274 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 275 |
|
|
i=i+1; ram[i] = 16'h36e8 ; // lo data
|
| 276 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 277 |
|
|
i=i+1; ram[i] = 16'ha53c ; // hi data
|
| 278 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 279 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 280 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 281 |
|
|
// ADD (s/b 'h01df,fa5f)
|
| 282 |
|
|
i=i+1; ram[i] = { op_add, `_, `_, `s2, `s1 }; // s1+s2=>s1
|
| 283 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 284 |
|
|
i=i+1; ram[i] = 16'hfa5f ; // lo data
|
| 285 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 286 |
|
|
i=i+1; ram[i] = 16'h01df ; // hi data
|
| 287 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 288 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 289 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 290 |
|
|
// ADD_X (s/b 0)
|
| 291 |
|
|
i=i+1; ram[i] = { op_add_x, `_, `_, `s2, `s1 }; // s1+s2=>s1
|
| 292 |
|
|
i=i+1; ram[i] = { `op_byt_i, 8'h0, `_, `_, `s0, `s0 }; // 0 => s0
|
| 293 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 294 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 295 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 296 |
|
|
// ADD_UX (s/b 1)
|
| 297 |
|
|
i=i+1; ram[i] = { op_add_ux, `_, `_, `s2, `s1 }; // s1+s2=>s1
|
| 298 |
|
|
i=i+1; ram[i] = { `op_byt_i, 8'h1, `_, `_, `s0, `s0 }; // 1 => s0
|
| 299 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 300 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 301 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 302 |
|
|
// SUB (s/b 'h4898,7333)
|
| 303 |
|
|
i=i+1; ram[i] = { op_sub, `_, `_, `s2, `s1 }; // s1-s2=>s1
|
| 304 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 305 |
|
|
i=i+1; ram[i] = 16'h7333 ; // lo data
|
| 306 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 307 |
|
|
i=i+1; ram[i] = 16'h4898 ; // hi data
|
| 308 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 309 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 310 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 311 |
|
|
// SUB_X (s/b -1)
|
| 312 |
|
|
i=i+1; ram[i] = { op_sub_x, `_, `_, `s2, `s1 }; // s1-s2=>s1
|
| 313 |
|
|
i=i+1; ram[i] = { `op_byt_i, -8'h1, `_, `_, `s0, `s0 }; // -1 => s0
|
| 314 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 315 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 316 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 317 |
|
|
// SUB_UX (s/b 0)
|
| 318 |
|
|
i=i+1; ram[i] = { op_sub_ux, `_, `_, `s2, `s1 }; // s1-s2=>s1
|
| 319 |
|
|
i=i+1; ram[i] = { `op_byt_i, 8'h0, `_, `_, `s0, `s0 }; // 0 => s0
|
| 320 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 321 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 322 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 323 |
|
|
// MUL (s/b 'hccfe,34c6)
|
| 324 |
|
|
i=i+1; ram[i] = { op_mul, `_, `_, `s2, `s1 }; // s1*s2=>s1
|
| 325 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 326 |
|
|
i=i+1; ram[i] = 16'h34c6 ; // lo data
|
| 327 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 328 |
|
|
i=i+1; ram[i] = 16'hccfe ; // hi data
|
| 329 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 330 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 331 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 332 |
|
|
// MUL_X (s/b 'hdf27,93ae)
|
| 333 |
|
|
i=i+1; ram[i] = { op_mul_x, `_, `_, `s2, `s1 }; // s1*s2=>s1
|
| 334 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 335 |
|
|
i=i+1; ram[i] = 16'h93ae ; // lo data
|
| 336 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 337 |
|
|
i=i+1; ram[i] = 16'hdf27 ; // hi data
|
| 338 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 339 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 340 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 341 |
|
|
// MUL_UX (s/b 'h3bcb,5744)
|
| 342 |
|
|
i=i+1; ram[i] = { op_mul_ux, `_, `_, `s2, `s1 }; // s1*s2=>s1
|
| 343 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 344 |
|
|
i=i+1; ram[i] = 16'h5744 ; // lo data
|
| 345 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 346 |
|
|
i=i+1; ram[i] = 16'h3bcb ; // hi data
|
| 347 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 348 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 349 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 350 |
|
|
// check for no opcode errors
|
| 351 |
|
|
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
|
| 352 |
|
|
i=i+1; ram[i] = 16'h900 ; // addr
|
| 353 |
|
|
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
|
| 354 |
|
|
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
|
| 355 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 356 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 357 |
|
|
// check for no stack errors
|
| 358 |
|
|
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
|
| 359 |
|
|
i=i+1; ram[i] = 16'h910 ; // addr
|
| 360 |
|
|
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
|
| 361 |
|
|
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
|
| 362 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 363 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 364 |
|
|
// s3=>s0, loop forever
|
| 365 |
|
|
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
|
| 366 |
|
|
i=i+1; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
// test ALU shift functions, result in s0
|
| 370 |
|
|
// Correct functioning is s0 = 'd10 ('ha).
|
| 371 |
|
|
//
|
| 372 |
|
|
// s0 : final test result
|
| 373 |
|
|
// s1 : test value
|
| 374 |
|
|
// s2 : test value
|
| 375 |
|
|
// s3 : running test result, subroutine return address
|
| 376 |
|
|
//
|
| 377 |
|
|
// setup running test result:
|
| 378 |
|
|
i='h300; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
|
| 379 |
|
|
// load s1 value 0xa53c36c9
|
| 380 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
|
| 381 |
|
|
i=i+1; ram[i] = 16'h36c9 ; // hi data
|
| 382 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
|
| 383 |
|
|
i=i+1; ram[i] = 16'ha53c ; // lo data
|
| 384 |
|
|
// SHL_I -28 (s/b 'hffff,fffa)
|
| 385 |
|
|
i=i+1; ram[i] = { `op_shl_i, -6'd28, `_, `_, `s1, `s1 }; // s1<<-28=>s1
|
| 386 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 387 |
|
|
i=i+1; ram[i] = 16'hfffa ; // lo data
|
| 388 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 389 |
|
|
i=i+1; ram[i] = 16'hffff ; // hi data
|
| 390 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 391 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 392 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 393 |
|
|
// SHL_I +28 (s/b 'h9000,0000)
|
| 394 |
|
|
i=i+1; ram[i] = { `op_shl_i, 6'd28, `_, `_, `s1, `s1 }; // s1<<28=>s1
|
| 395 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 396 |
|
|
i=i+1; ram[i] = 16'h0000 ; // lo data
|
| 397 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 398 |
|
|
i=i+1; ram[i] = 16'h9000 ; // hi data
|
| 399 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 400 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 401 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 402 |
|
|
// SHL_IU -28 (s/b 'h0000,000a)
|
| 403 |
|
|
i=i+1; ram[i] = { `op_shl_iu, -6'd28, `_, `_, `s1, `s1 }; // s1<<-28=>s1
|
| 404 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 405 |
|
|
i=i+1; ram[i] = 16'h000a ; // lo data
|
| 406 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 407 |
|
|
i=i+1; ram[i] = 16'h0000 ; // hi data
|
| 408 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 409 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 410 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 411 |
|
|
// SHL_IU +28 (s/b 'h1000,0000)
|
| 412 |
|
|
i=i+1; ram[i] = { `op_shl_iu, 6'd28, `_, `_, `s1, `s1 }; // 1<<28=>s1
|
| 413 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 414 |
|
|
i=i+1; ram[i] = 16'h0000 ; // lo data
|
| 415 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 416 |
|
|
i=i+1; ram[i] = 16'h1000 ; // hi data
|
| 417 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 418 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 419 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 420 |
|
|
// SHL -4 (s/b 'hfa53,c36c)
|
| 421 |
|
|
i=i+1; ram[i] = { `op_byt_i, -8'd4, `_, `_, `s2, `s2 }; // -4=>s2
|
| 422 |
|
|
i=i+1; ram[i] = { op_shl, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
|
| 423 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 424 |
|
|
i=i+1; ram[i] = 16'hc36c ; // lo data
|
| 425 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 426 |
|
|
i=i+1; ram[i] = 16'hfa53 ; // hi data
|
| 427 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 428 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 429 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 430 |
|
|
// SHL +4 (s/b 'h53c3,6c90)
|
| 431 |
|
|
i=i+1; ram[i] = { `op_byt_i, 8'd4, `_, `_, `s2, `s2 }; // 4=>s2
|
| 432 |
|
|
i=i+1; ram[i] = { op_shl, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
|
| 433 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 434 |
|
|
i=i+1; ram[i] = 16'h6c90 ; // lo data
|
| 435 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 436 |
|
|
i=i+1; ram[i] = 16'h53c3 ; // hi data
|
| 437 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 438 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 439 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 440 |
|
|
// SHL_U -4 (s/b 'h0a53,c36c)
|
| 441 |
|
|
i=i+1; ram[i] = { `op_byt_i, -8'd4, `_, `_, `s2, `s2 }; // -4=>s2
|
| 442 |
|
|
i=i+1; ram[i] = { op_shl_u, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
|
| 443 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 444 |
|
|
i=i+1; ram[i] = 16'hc36c ; // lo data
|
| 445 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 446 |
|
|
i=i+1; ram[i] = 16'h0a53 ; // hi data
|
| 447 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 448 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 449 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 450 |
|
|
// SHL +4 (s/b 'h0000,0010)
|
| 451 |
|
|
i=i+1; ram[i] = { `op_byt_i, 8'd4, `_, `_, `s2, `s2 }; // 4=>s2
|
| 452 |
|
|
i=i+1; ram[i] = { op_shl_u, `P, `_, `s2, `s1 }; // 1<<s2=>s1, pop s2
|
| 453 |
|
|
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
|
| 454 |
|
|
i=i+1; ram[i] = 16'h0010 ; // lo data
|
| 455 |
|
|
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
|
| 456 |
|
|
i=i+1; ram[i] = 16'h0000 ; // hi data
|
| 457 |
|
|
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
|
| 458 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 459 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 460 |
|
|
// check for no opcode errors
|
| 461 |
|
|
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
|
| 462 |
|
|
i=i+1; ram[i] = 16'h900 ; // addr
|
| 463 |
|
|
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
|
| 464 |
|
|
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
|
| 465 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 466 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 467 |
|
|
// check for no stack errors
|
| 468 |
|
|
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
|
| 469 |
|
|
i=i+1; ram[i] = 16'h910 ; // addr
|
| 470 |
|
|
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
|
| 471 |
|
|
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
|
| 472 |
|
|
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
|
| 473 |
|
|
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
|
| 474 |
|
|
// s3=>s0, loop forever
|
| 475 |
|
|
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
|
| 476 |
|
|
i=i+1; ram[i] = { `op_jmp_i, -5'h1, `_, `_, `s0, `s0 }; // loop forever
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
|
|
|
| 480 |
|
|
|
| 481 |
|
|
/////////////////
|
| 482 |
|
|
// subroutines //
|
| 483 |
|
|
/////////////////
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
// sub : read & clear opcode errors for this thread => s0, return to (s3)
|
| 487 |
|
|
i='h900; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
|
| 488 |
|
|
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
|
| 489 |
|
|
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
|
| 490 |
|
|
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
|
| 491 |
|
|
i=i+1; ram[i] = { `op_rd_i, OP_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
|
| 492 |
|
|
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
|
| 493 |
|
|
i=i+1; ram[i] = { `op_wr_i, OP_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
|
| 494 |
|
|
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
|
| 495 |
|
|
|
| 496 |
|
|
|
| 497 |
|
|
// sub : read & clear stack errors for this thread => s0, return to (s3)
|
| 498 |
|
|
i='h910; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
|
| 499 |
|
|
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
|
| 500 |
|
|
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
|
| 501 |
|
|
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
|
| 502 |
|
|
i=i+1; ram[i] = { op_cpy, `_, `_, `s0, `s3 }; // s0=>s3
|
| 503 |
|
|
i=i+1; ram[i] = { `op_shl_i, 6'd8, `_, `P, `s0, `s3 }; // s3<<8=>s3, pop s3
|
| 504 |
|
|
i=i+1; ram[i] = { op_or, `P, `P, `s3, `s0 }; // s0|s3=>s0, pop both
|
| 505 |
|
|
i=i+1; ram[i] = { `op_rd_i, STK_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
|
| 506 |
|
|
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
|
| 507 |
|
|
i=i+1; ram[i] = { `op_wr_i, STK_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
|
| 508 |
|
|
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
|
| 509 |
|
|
|
| 510 |
|
|
|
| 511 |
|
|
|
| 512 |
|
|
end
|
