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/*
--------------------------------------------------------------------------------
 
Module : data_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor data path & data stacks.
 
Instantiates:
- (1x) stacks_mux.v
- (1x) alu_top.v
- (1x) pointer_ring.v
- (4x) dq_ram_infer.v
 
Notes:
- 8 stage data pipeline beginning and ending on four BRAM based LIFOs.
 
--------------------------------------------------------------------------------
*/
 
module data_ring
        #(
        parameter       integer                                                 DATA_W                  = 32,           // data width
        parameter       integer                                                 ADDR_W                  = 16,           // address width
        parameter       integer                                                 THREADS                 = 8,            // threads
        parameter       integer                                                 THRD_W                  = 3,            // thread selector width
        parameter       integer                                                 STACKS                  = 4,            // stacks
        parameter       integer                                                 STK_W                           = 2,            // stack selector width
        parameter       integer                                                 PNTR_W                  = 5,            // stack pointer width
        parameter       integer                                                 IM_DATA_W               = 8,            // immediate data width
        parameter       integer                                                 LG_W                            = 2,            // operation width
        parameter       integer                                                 POP_PROT                        = 1,            // 1=error protection, 0=none
        parameter       integer                                                 PUSH_PROT               = 1             // 1=error protection, 0=none
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // control I/O
        input                   wire    [STK_W-1:0]                              a_sel_i,                                                // stack selector
        input                   wire    [STK_W-1:0]                              b_sel_i,                                                // stack selector
        input                   wire                                                            imda_i,                                         // 1=immediate data
        input                   wire                                                            sgn_i,                                          // 1=signed
        input                   wire                                                            ext_i,                                          // 1=extended result
        input                   wire    [LG_W-1:0]                               lg_i,                                                   // see decode in notes above
        input                   wire                                                            add_i,                                          // 1=add
        input                   wire                                                            sub_i,                                          // 1=subtract
        input                   wire                                                            mul_i,                                          // 1=multiply
        input                   wire                                                            shl_i,                                          // 1=shift left
        input                   wire                                                            cpy_i,                                          // 1=copy b
        input                   wire                                                            dm_i,                                                   // 1=data mem
        input                   wire                                                            rtn_i,                                          // 1=return pc
        // stack I/O
        input                   wire                                                            stk_clr_i,                                      // stacks clear
        input                   wire    [STACKS-1:0]                     pop_i,                                          // stacks pop
        input                   wire    [STACKS-1:0]                     push_i,                                         // stacks push
        input                   wire    [THRD_W-1:0]                     thrd_6_i,                                       // thread
        // data I/O
        input                   wire    [IM_DATA_W-1:0]          im_data_i,                                      // immediate data
        input                   wire    [DATA_W/2-1:0]                   dm_data_i,                                      // dmem read data
        input                   wire    [ADDR_W-1:0]                     pc_3_i,                                         // program counter
        output          wire    [DATA_W-1:0]                     a_o,                                                    // a
        output          wire    [DATA_W-1:0]                     b_o,                                                    // b
        // flags
        output          wire                                                            nez_o,                                          //      a != 0
        output          wire                                                            ne_o,                                                   //      a != b
        output          wire                                                            ltz_o,                                          //      a < 0
        output          wire                                                            lt_o,                                                   //      a < b
        // errors
        output          wire    [STACKS-1:0]                     pop_er_o,                                       // pop when empty, active high 
        output          wire    [STACKS-1:0]                     push_er_o                                       // push when full, active high
        );
 
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        wire                                    [DATA_W-1:0]                     b_alu;
        wire                                    [DATA_W-1:0]                     pop_data0, pop_data1, pop_data2, pop_data3, push_data;
        wire                                    [PNTR_W-1:0]                     pntr0, pntr1, pntr2, pntr3;
        wire                                    [STACKS-1:0]                     stk_wr;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
 
        // stacks output mux
        stacks_mux
        #(
        .DATA_W                 ( DATA_W ),
        .STK_W                  ( STK_W ),
        .IM_DATA_W              ( IM_DATA_W )
        )
        stacks_mux
        (
        .a_sel_i                        ( a_sel_i ),
        .b_sel_i                        ( b_sel_i ),
        .imda_i                 ( imda_i ),
        .pop_data0_i    ( pop_data0 ),
        .pop_data1_i    ( pop_data1 ),
        .pop_data2_i    ( pop_data2 ),
        .pop_data3_i    ( pop_data3 ),
        .im_data_i              ( im_data_i ),
        .a_o                            ( a_o ),
        .b_o                            ( b_o ),
        .b_alu_o                        ( b_alu )
        );
 
 
        // ALU
        alu_top
        #(
        .REGS_IN                        ( 1 ),
        .REGS_OUT               ( 1 ),
        .REGS_FLG               ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( ADDR_W ),
        .LG_W                           ( LG_W )
        )
        alu_top
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .sgn_i                  ( sgn_i ),
        .ext_i                  ( ext_i ),
        .lg_i                           ( lg_i ),
        .add_i                  ( add_i ),
        .sub_i                  ( sub_i ),
        .mul_i                  ( mul_i ),
        .shl_i                  ( shl_i ),
        .cpy_i                  ( cpy_i ),
        .dm_i                           ( dm_i ),
        .rtn_i                  ( rtn_i ),
        .a_i                            ( a_o ),
        .b_i                            ( b_alu ),
        .dm_data_i              ( dm_data_i ),
        .pc_3_i                 ( pc_3_i ),
        .result_o               ( push_data ),
        .nez_o                  ( nez_o ),
        .ne_o                           ( ne_o ),
        .ltz_o                  ( ltz_o ),
        .lt_o                           ( lt_o )
        );
 
 
        // stack pointer generation & storage
        pointer_ring
        #(
        .THREADS                        ( THREADS ),
        .STACKS                 ( STACKS ),
        .PNTR_W                 ( PNTR_W ),
        .POP_PROT               ( POP_PROT ),
        .PUSH_PROT              ( PUSH_PROT )
        )
        pointer_ring
        (
        .clk_i                  ( clk_i ),
        .rst_i                  ( rst_i ),
        .clr_i                  ( stk_clr_i ),
        .pop_i                  ( pop_i ),
        .push_i                 ( push_i ),
        .pntr0_o                        ( pntr0 ),
        .pntr1_o                        ( pntr1 ),
        .pntr2_o                        ( pntr2 ),
        .pntr3_o                        ( pntr3 ),
        .wr_o                           ( stk_wr ),
        .pop_er_o               ( pop_er_o ),
        .push_er_o              ( push_er_o )
        );
 
 
        // LIFO stacks memory
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .RD_MODE                ( "WR_DATA" )
        )
        stack0_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr0 } ),
        .wr_i                           ( stk_wr[0] ),
        .data_i                 ( push_data ),
        .data_o                 ( pop_data0 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .RD_MODE                ( "WR_DATA" )
        )
        stack1_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr1 } ),
        .wr_i                           ( stk_wr[1] ),
        .data_i                 ( push_data ),
        .data_o                 ( pop_data1 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .RD_MODE                ( "WR_DATA" )
        )
        stack2_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr2 } ),
        .wr_i                           ( stk_wr[2] ),
        .data_i                 ( push_data ),
        .data_o                 ( pop_data2 )
        );
 
 
        dq_ram_infer
        #(
        .REG_OUT                        ( 1 ),
        .DATA_W                 ( DATA_W ),
        .ADDR_W                 ( THRD_W+PNTR_W ),
        .RD_MODE                ( "WR_DATA" )
        )
        stack3_dq_ram
        (
        .clk_i                  ( clk_i ),
        .addr_i                 ( { thrd_6_i, pntr3 } ),
        .wr_i                           ( stk_wr[3] ),
        .data_i                 ( push_data ),
        .data_o                 ( pop_data3 )
        );
 
endmodule

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[/] [hive/] [trunk/] [v01.10/] [data_ring.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	3	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : data_ring.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Processor data path & data stacks.`
10
11			`Instantiates:`
12			`- (1x) stacks_mux.v`
13			`- (1x) alu_top.v`
14			`- (1x) pointer_ring.v`
15			`- (4x) dq_ram_infer.v`
16
17			`Notes:`
18			`- 8 stage data pipeline beginning and ending on four BRAM based LIFOs.`
19
20			`--------------------------------------------------------------------------------`
21			`*/`
22
23			`module data_ring`
24			`#(`
25			`parameter integer DATA_W = 32, // data width`
26			`parameter integer ADDR_W = 16, // address width`
27			`parameter integer THREADS = 8, // threads`
28			`parameter integer THRD_W = 3, // thread selector width`
29			`parameter integer STACKS = 4, // stacks`
30			`parameter integer STK_W = 2, // stack selector width`
31			`parameter integer PNTR_W = 5, // stack pointer width`
32			`parameter integer IM_DATA_W = 8, // immediate data width`
33			`parameter integer LG_W = 2, // operation width`
34			`parameter integer POP_PROT = 1, // 1=error protection, 0=none`
35			`parameter integer PUSH_PROT = 1 // 1=error protection, 0=none`
36			`)`
37			`(`
38			`// clocks & resets`
39			`input wire clk_i, // clock`
40			`input wire rst_i, // async. reset, active high`
41			`// control I/O`
42			`input wire [STK_W-1:0] a_sel_i, // stack selector`
43			`input wire [STK_W-1:0] b_sel_i, // stack selector`
44			`input wire imda_i, // 1=immediate data`
45			`input wire sgn_i, // 1=signed`
46			`input wire ext_i, // 1=extended result`
47			`input wire [LG_W-1:0] lg_i, // see decode in notes above`
48			`input wire add_i, // 1=add`
49			`input wire sub_i, // 1=subtract`
50			`input wire mul_i, // 1=multiply`
51			`input wire shl_i, // 1=shift left`
52			`input wire cpy_i, // 1=copy b`
53			`input wire dm_i, // 1=data mem`
54			`input wire rtn_i, // 1=return pc`
55			`// stack I/O`
56			`input wire stk_clr_i, // stacks clear`
57			`input wire [STACKS-1:0] pop_i, // stacks pop`
58			`input wire [STACKS-1:0] push_i, // stacks push`
59			`input wire [THRD_W-1:0] thrd_6_i, // thread`
60			`// data I/O`
61			`input wire [IM_DATA_W-1:0] im_data_i, // immediate data`
62			`input wire [DATA_W/2-1:0] dm_data_i, // dmem read data`
63			`input wire [ADDR_W-1:0] pc_3_i, // program counter`
64			`output wire [DATA_W-1:0] a_o, // a`
65			`output wire [DATA_W-1:0] b_o, // b`
66			`// flags`
67			`output wire nez_o, // a != 0`
68			`output wire ne_o, // a != b`
69			`output wire ltz_o, // a < 0`
70			`output wire lt_o, // a < b`
71			`// errors`
72			`output wire [STACKS-1:0] pop_er_o, // pop when empty, active high`
73			`output wire [STACKS-1:0] push_er_o // push when full, active high`
74			`);`
75
76
77
78			`/*`
79			`----------------------`
80			`-- internal signals --`
81			`----------------------`
82			`*/`
83			`wire [DATA_W-1:0] b_alu;`
84			`wire [DATA_W-1:0] pop_data0, pop_data1, pop_data2, pop_data3, push_data;`
85			`wire [PNTR_W-1:0] pntr0, pntr1, pntr2, pntr3;`
86			`wire [STACKS-1:0] stk_wr;`
87
88
89
90			`/*`
91			`================`
92			`== code start ==`
93			`================`
94			`*/`
95
96
97
98			`// stacks output mux`
99			`stacks_mux`
100			`#(`
101			`.DATA_W ( DATA_W ),`
102			`.STK_W ( STK_W ),`
103			`.IM_DATA_W ( IM_DATA_W )`
104			`)`
105			`stacks_mux`
106			`(`
107			`.a_sel_i ( a_sel_i ),`
108			`.b_sel_i ( b_sel_i ),`
109			`.imda_i ( imda_i ),`
110			`.pop_data0_i ( pop_data0 ),`
111			`.pop_data1_i ( pop_data1 ),`
112			`.pop_data2_i ( pop_data2 ),`
113			`.pop_data3_i ( pop_data3 ),`
114			`.im_data_i ( im_data_i ),`
115			`.a_o ( a_o ),`
116			`.b_o ( b_o ),`
117			`.b_alu_o ( b_alu )`
118			`);`
119
120
121			`// ALU`
122			`alu_top`
123			`#(`
124			`.REGS_IN ( 1 ),`
125			`.REGS_OUT ( 1 ),`
126			`.REGS_FLG ( 1 ),`
127			`.DATA_W ( DATA_W ),`
128			`.ADDR_W ( ADDR_W ),`
129			`.LG_W ( LG_W )`
130			`)`
131			`alu_top`
132			`(`
133			`.clk_i ( clk_i ),`
134			`.rst_i ( rst_i ),`
135			`.sgn_i ( sgn_i ),`
136			`.ext_i ( ext_i ),`
137			`.lg_i ( lg_i ),`
138			`.add_i ( add_i ),`
139			`.sub_i ( sub_i ),`
140			`.mul_i ( mul_i ),`
141			`.shl_i ( shl_i ),`
142			`.cpy_i ( cpy_i ),`
143			`.dm_i ( dm_i ),`
144			`.rtn_i ( rtn_i ),`
145			`.a_i ( a_o ),`
146			`.b_i ( b_alu ),`
147			`.dm_data_i ( dm_data_i ),`
148			`.pc_3_i ( pc_3_i ),`
149			`.result_o ( push_data ),`
150			`.nez_o ( nez_o ),`
151			`.ne_o ( ne_o ),`
152			`.ltz_o ( ltz_o ),`
153			`.lt_o ( lt_o )`
154			`);`
155
156
157			`// stack pointer generation & storage`
158			`pointer_ring`
159			`#(`
160			`.THREADS ( THREADS ),`
161			`.STACKS ( STACKS ),`
162			`.PNTR_W ( PNTR_W ),`
163			`.POP_PROT ( POP_PROT ),`
164			`.PUSH_PROT ( PUSH_PROT )`
165			`)`
166			`pointer_ring`
167			`(`
168			`.clk_i ( clk_i ),`
169			`.rst_i ( rst_i ),`
170			`.clr_i ( stk_clr_i ),`
171			`.pop_i ( pop_i ),`
172			`.push_i ( push_i ),`
173			`.pntr0_o ( pntr0 ),`
174			`.pntr1_o ( pntr1 ),`
175			`.pntr2_o ( pntr2 ),`
176			`.pntr3_o ( pntr3 ),`
177			`.wr_o ( stk_wr ),`
178			`.pop_er_o ( pop_er_o ),`
179			`.push_er_o ( push_er_o )`
180			`);`
181
182
183			`// LIFO stacks memory`
184			`dq_ram_infer`
185			`#(`
186			`.REG_OUT ( 1 ),`
187			`.DATA_W ( DATA_W ),`
188			`.ADDR_W ( THRD_W+PNTR_W ),`
189			`.RD_MODE ( "WR_DATA" )`
190			`)`
191			`stack0_dq_ram`
192			`(`
193			`.clk_i ( clk_i ),`
194			`.addr_i ( { thrd_6_i, pntr0 } ),`
195			`.wr_i ( stk_wr[0] ),`
196			`.data_i ( push_data ),`
197			`.data_o ( pop_data0 )`
198			`);`
199
200
201			`dq_ram_infer`
202			`#(`
203			`.REG_OUT ( 1 ),`
204			`.DATA_W ( DATA_W ),`
205			`.ADDR_W ( THRD_W+PNTR_W ),`
206			`.RD_MODE ( "WR_DATA" )`
207			`)`
208			`stack1_dq_ram`
209			`(`
210			`.clk_i ( clk_i ),`
211			`.addr_i ( { thrd_6_i, pntr1 } ),`
212			`.wr_i ( stk_wr[1] ),`
213			`.data_i ( push_data ),`
214			`.data_o ( pop_data1 )`
215			`);`
216
217
218			`dq_ram_infer`
219			`#(`
220			`.REG_OUT ( 1 ),`
221			`.DATA_W ( DATA_W ),`
222			`.ADDR_W ( THRD_W+PNTR_W ),`
223			`.RD_MODE ( "WR_DATA" )`
224			`)`
225			`stack2_dq_ram`
226			`(`
227			`.clk_i ( clk_i ),`
228			`.addr_i ( { thrd_6_i, pntr2 } ),`
229			`.wr_i ( stk_wr[2] ),`
230			`.data_i ( push_data ),`
231			`.data_o ( pop_data2 )`
232			`);`
233
234
235			`dq_ram_infer`
236			`#(`
237			`.REG_OUT ( 1 ),`
238			`.DATA_W ( DATA_W ),`
239			`.ADDR_W ( THRD_W+PNTR_W ),`
240			`.RD_MODE ( "WR_DATA" )`
241			`)`
242			`stack3_dq_ram`
243			`(`
244			`.clk_i ( clk_i ),`
245			`.addr_i ( { thrd_6_i, pntr3 } ),`
246			`.wr_i ( stk_wr[3] ),`
247			`.data_i ( push_data ),`
248			`.data_o ( pop_data3 )`
249			`);`
250
251			`endmodule`