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ericw |
/*
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--------------------------------------------------------------------------------
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Module : op_decode.v
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--------------------------------------------------------------------------------
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Function:
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- Opcode decoder for processor.
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Instantiates:
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- (2x) vector_sr.v
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Notes:
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- I/O optionally registered.
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- Middle register is always present.
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- Operates on the current thread in the stage.
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--------------------------------------------------------------------------------
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*/
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module op_decode
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#(
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parameter integer REGS_IN = 1, // register option for inputs
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parameter integer REGS_OUT = 1, // register option for outputs
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parameter integer STACKS = 4, // number of stacks
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parameter integer STK_W = 2, // stack selector width
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parameter integer DATA_W = 32, // data width
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parameter integer IM_DATA_W = 8, // immediate data width
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parameter integer IM_ADDR_W = 5, // immediate address width
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parameter integer OP_CODE_W = 16, // op code width
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parameter integer LG_W = 2 // logical operation width
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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// state I/O
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input wire thrd_clr_i, // thread clear
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input wire thrd_intr_i, // thread interrupt
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input wire [OP_CODE_W-1:0] op_code_i, // op_code
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output wire op_code_er_o, // 1=illegal op code encountered
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// data I/O
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output wire [IM_DATA_W-1:0] im_data_o, // immediate data
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output wire [IM_ADDR_W-1:0] im_addr_o, // immediate address (offset)
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// pc pipe control
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output wire pc_clr_o, // pc clear
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output wire lit_o, // 1 : pc=pc++ for lit
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output wire jmp_o, // 1 : pc=pc+B for jump (cond)
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output wire gto_o, // 1 : pc=B for goto / gosub (cond)
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output wire intr_o, // 1 : pc=intr
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// conditional masks
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output wire tst_eq_o, // = test
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output wire tst_lt_o, // < test
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output wire tst_gt_o, // > test
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output wire tst_ab_o, // 1=a/b test; 0=a/z test
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// stacks control
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output wire stk_clr_o, // stacks clear
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output wire [STACKS-1:0] pop_o, // stacks pop
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output wire [STACKS-1:0] push_o, // stacks push
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// alu control
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output wire [STK_W-1:0] a_sel_o, // stack selector
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output wire [STK_W-1:0] b_sel_o, // stack selector
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output wire imda_o, // 1=immediate data
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output wire imad_o, // 1=immediate address
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output wire sgn_o, // 1=signed
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output wire ext_o, // 1=extended
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output wire [LG_W-1:0] lg_o, // see decode in notes
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output wire add_o, // 1=add
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output wire sub_o, // 1=subtract
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output wire mul_o, // 1=multiply
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output wire shl_o, // 1=shift left
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output wire cpy_o, // 1=copy b
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output wire dm_o, // 1=data mem
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output wire rtn_o, // 1=return pc
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output wire rd_o, // 1=read
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output wire wr_o // 1=write
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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`include "op_encode.h"
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wire thrd_clr, thrd_intr;
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wire [OP_CODE_W-1:0] op_code;
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reg op_ok, op_code_ok_lo, op_code_ok_hi;
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wire op_code_er;
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//
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reg [IM_DATA_W-1:0] im_data;
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wire [IM_ADDR_W-1:0] im_addr;
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reg pc_clr;
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reg intr, gto, jmp, lit;
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reg tst_lo, tst_hi, tst_ab, tst_gt, tst_lt, tst_eq;
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reg stk_clr;
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reg a_pop, b_pop;
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reg push_lo, push_hi;
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wire [STACKS-1:0] pop, push;
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reg [STK_W-1:0] a_sel, b_sel;
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reg imad_5b;
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reg imda_8b, imda_6b;
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wire imad, imda;
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reg rtn, dm, cpy, shl, mul, sub, add, ext, sgn;
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reg [LG_W-1:0] lg;
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reg rd, wr;
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/*
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================
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== code start ==
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================
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*/
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// optional input registers
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vector_sr
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#(
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.REGS ( REGS_IN ),
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.DATA_W ( 2+OP_CODE_W ),
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.RESET_VAL ( 0 )
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)
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in_regs
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.data_i ( { thrd_clr_i, thrd_intr_i, op_code_i } ),
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.data_o ( { thrd_clr, thrd_intr, op_code } )
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);
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// instantiate & split out op_code fields
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wire [1:0] op_code_a_sel = op_code[1:0];
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wire [1:0] op_code_b_sel = op_code[3:2];
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wire op_code_a_pop = op_code[4];
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wire op_code_b_pop = op_code[5];
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wire [9:0] op_code_op = op_code[15:6];
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wire [2:0] op_code_tst_hi = op_code[13:11];
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wire [2:0] op_code_tst_lo = op_code[8:6];
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wire [7:0] op_code_im = op_code[13:6];
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//
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reg [2:0] tst_hi_field, tst_lo_field;
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reg [7:0] im_field;
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// mid register for immediate and test fields
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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tst_hi_field <= 'b0;
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tst_lo_field <= 'b0;
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im_field <= 'b0;
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end else begin
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tst_hi_field <= op_code_tst_hi;
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tst_lo_field <= op_code_tst_lo;
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im_field <= op_code_im;
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end
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end
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// mid register if & case: clear, interrupt, and op_code decode
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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op_ok <= 'b0;
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op_code_ok_lo <= 'b0;
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op_code_ok_hi <= 'b0;
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pc_clr <= 'b0;
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lit <= 'b0;
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jmp <= 'b0;
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gto <= 'b0;
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intr <= 'b0;
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tst_hi <= 'b0;
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tst_lo <= 'b0;
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tst_ab <= 'b0;
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stk_clr <= 'b0;
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a_pop <= 'b0;
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b_pop <= 'b0;
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push_lo <= 'b0;
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push_hi <= 'b0;
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a_sel <= 'b0;
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b_sel <= 'b0;
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imad_5b <= 'b0;
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imda_8b <= 'b0;
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imda_6b <= 'b0;
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sgn <= 'b0;
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ext <= 'b0;
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lg <= 'b0;
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add <= 'b0;
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sub <= 'b0;
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mul <= 'b0;
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shl <= 'b0;
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cpy <= 'b0;
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dm <= 'b0;
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rtn <= 'b0;
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rd <= 'b0;
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wr <= 'b0;
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end else begin
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// default values
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op_ok <= 'b0; // default is bad op
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op_code_ok_lo <= 'b0; // default is bad opcode
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op_code_ok_hi <= 'b0; // default is bad opcode
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pc_clr <= 'b0; // default is no pc clear
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lit <= 'b0; // default is no lit
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jmp <= 'b0; // default is no jump
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gto <= 'b0; // default is no goto
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intr <= 'b0; // default is no interrupt
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tst_hi <= 'b0; // default is no test
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tst_lo <= 'b0; // default is no test
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tst_ab <= 'b0; // default is comparison to zero
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stk_clr <= 'b0; // default is no stack clear
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a_pop <= op_code_a_pop; // default is op_code directive
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b_pop <= op_code_b_pop; // default is op_code directive
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push_lo <= 'b0; // default is no push
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push_hi <= 'b0; // default is no push
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a_sel <= op_code_a_sel; // default is op_code directive
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b_sel <= op_code_b_sel; // default is op_code directive
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imad_5b <= 'b0; // default is not immediate address
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imda_8b <= 'b0; // default is not immediate data
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imda_6b <= 'b0; // default is not immediate data
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sgn <= 'b1; // default is signed!
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ext <= 'b0; // default is unextended
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lg <= 'b0; // default is a&b
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add <= 'b0; // default is logic
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sub <= 'b0; // default is logic
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mul <= 'b0; // default is logic
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shl <= 'b0; // default is logic
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cpy <= 'b0; // default is logic
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dm <= 'b0; // default is logic
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rtn <= 'b0; // default is logic
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rd <= 'b0; // default is don't read
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wr <= 'b0; // default is don't write
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if ( thrd_clr ) begin
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op_ok <= 'b1; // good op
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pc_clr <= 'b1; // clear pc
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stk_clr <= 'b1; // clear stacks
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a_pop <= 'b0; // no pop
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b_pop <= 'b0; // no pop
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end else if ( thrd_intr ) begin
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op_ok <= 'b1; // good op
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intr <= 'b1; // don't inc PC
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a_pop <= 'b0; // no pop
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b_pop <= 'b0; // no pop
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push_lo <= 'b1; // push
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a_sel <= 'b0; // push return address to stack 0
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rtn <= 'b1; // push pc
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end else begin
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casex ( op_code_op )
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///////////////////////////////
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// immediate read - 32 codes //
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///////////////////////////////
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op_rd_i : begin
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op_code_ok_lo <= 'b1; // good opcode
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push_lo <= 'b1; // push
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dm <= 'b1; // dm
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rd <= 'b1; // read
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end
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op_rd_ix : begin
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op_code_ok_lo <= 'b1; // good opcode
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push_lo <= 'b1; // push
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dm <= 'b1; // dm
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rd <= 'b1; // read
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ext <= 'b1; // extended
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end
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////////////////////////////////////////////
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// immediate conditional jump - 224 codes //
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////////////////////////////////////////////
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op_jmp_iez, op_jmp_ilz, op_jmp_ilez : begin
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op_code_ok_lo <= 'b1; // good opcode
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jmp <= 'b1; // jump
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imad_5b <= 'b1; // immediate address
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tst_hi <= 'b1; // high field
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end
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op_jmp_igz, op_jmp_igez, op_jmp_iglz, op_jmp_i : begin
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op_code_ok_lo <= 'b1; // good opcode
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jmp <= 'b1; // jump
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imad_5b <= 'b1; // immediate address
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tst_hi <= 'b1; // high field
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end
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////////////////////////////////
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// immediate write - 32 codes //
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////////////////////////////////
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op_wr_i : begin
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op_code_ok_lo <= 'b1; // good opcode
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wr <= 'b1; // write
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end
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op_wr_ix : begin
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op_code_ok_lo <= 'b1; // good opcode
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wr <= 'b1; // write
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ext <= 'b1; // extended
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end
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////////////////////////////////////////////
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// immediate conditional jump - 192 codes //
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////////////////////////////////////////////
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op_jmp_ie, op_jmp_il, op_jmp_ile : begin
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op_code_ok_lo <= 'b1; // good opcode
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jmp <= 'b1; // jump
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imad_5b <= 'b1; // immediate address
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tst_hi <= 'b1; // high field
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tst_ab <= 'b1; // a & b comparison
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end
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op_jmp_iug, op_jmp_iuge, op_jmp_igl : begin // gl is sign neutral
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op_code_ok_lo <= 'b1; // good opcode
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jmp <= 'b1; // jump
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imad_5b <= 'b1; // immediate address
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tst_hi <= 'b1; // high field
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tst_ab <= 'b1; // a & b comparison
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sgn <= 'b0; // unsigned
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end
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///////////////////////
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// unused - 32 codes //
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///////////////////////
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////////////////////////////////
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// immediate data - 256 codes //
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////////////////////////////////
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op_byt_i : begin
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op_code_ok_lo <= 'b1; // good opcode
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push_lo <= 'b1; // push
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imda_8b <= 'b1; // immediate data
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cpy <= 'b1; // copy
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end
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/////////////////////////////////
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// immediate shift - 128 codes //
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/////////////////////////////////
|
| 324 |
|
|
op_shl_i : begin
|
| 325 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 326 |
|
|
push_lo <= 'b1; // push
|
| 327 |
|
|
imda_6b <= 'b1; // immediate data
|
| 328 |
|
|
shl <= 'b1; // shift left
|
| 329 |
|
|
end
|
| 330 |
|
|
op_shl_iu : begin
|
| 331 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 332 |
|
|
push_lo <= 'b1; // push
|
| 333 |
|
|
imda_6b <= 'b1; // immediate data
|
| 334 |
|
|
shl <= 'b1; // shift left
|
| 335 |
|
|
sgn <= 'b0; // unsigned
|
| 336 |
|
|
end
|
| 337 |
|
|
//////////////////////////////
|
| 338 |
|
|
// immediate add - 64 codes //
|
| 339 |
|
|
//////////////////////////////
|
| 340 |
|
|
op_add_i : begin
|
| 341 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 342 |
|
|
push_hi <= 'b1; // push
|
| 343 |
|
|
imda_6b <= 'b1; // immediate data
|
| 344 |
|
|
add <= 'b1; // add
|
| 345 |
|
|
end
|
| 346 |
|
|
/////////////////////////////////////
|
| 347 |
|
|
// conditional jump - 7 of 8 codes //
|
| 348 |
|
|
/////////////////////////////////////
|
| 349 |
|
|
op_jmp_ez, op_jmp_lz, op_jmp_lez, op_jmp_gz, op_jmp_gez, op_jmp_glz, op_jmp : begin
|
| 350 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 351 |
|
|
jmp <= 'b1; // jump
|
| 352 |
|
|
tst_lo <= 'b1; // low field
|
| 353 |
|
|
end
|
| 354 |
|
|
/////////////////////////////////////
|
| 355 |
|
|
// conditional goto - 7 of 8 codes //
|
| 356 |
|
|
/////////////////////////////////////
|
| 357 |
|
|
op_gto_ez, op_gto_lz, op_gto_lez, op_gto_gz, op_gto_gez, op_gto_glz, op_gto : begin
|
| 358 |
|
|
op_code_ok_lo <= 'b1; // good opcode
|
| 359 |
|
|
gto <= 'b1; // goto
|
| 360 |
|
|
tst_lo <= 'b1; // low field
|
| 361 |
|
|
end
|
| 362 |
|
|
////////////////////////
|
| 363 |
|
|
// singles - 48 codes //
|
| 364 |
|
|
////////////////////////
|
| 365 |
|
|
/////////////
|
| 366 |
|
|
// group 1 //
|
| 367 |
|
|
/////////////
|
| 368 |
|
|
op_add : begin
|
| 369 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 370 |
|
|
push_hi <= 'b1; // push
|
| 371 |
|
|
add <= 'b1; // add
|
| 372 |
|
|
end
|
| 373 |
|
|
op_add_x : begin
|
| 374 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 375 |
|
|
push_hi <= 'b1; // push
|
| 376 |
|
|
add <= 'b1; // add
|
| 377 |
|
|
ext <= 'b1; // extended
|
| 378 |
|
|
end
|
| 379 |
|
|
op_add_ux : begin
|
| 380 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 381 |
|
|
push_hi <= 'b1; // push
|
| 382 |
|
|
add <= 'b1; // add
|
| 383 |
|
|
ext <= 'b1; // extended
|
| 384 |
|
|
sgn <= 'b0; // unsigned
|
| 385 |
|
|
end
|
| 386 |
|
|
op_sub : begin
|
| 387 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 388 |
|
|
push_hi <= 'b1; // push
|
| 389 |
|
|
sub <= 'b1; // sub
|
| 390 |
|
|
end
|
| 391 |
|
|
op_sub_x : begin
|
| 392 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 393 |
|
|
push_hi <= 'b1; // push
|
| 394 |
|
|
sub <= 'b1; // sub
|
| 395 |
|
|
ext <= 'b1; // extended
|
| 396 |
|
|
end
|
| 397 |
|
|
op_sub_ux : begin
|
| 398 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 399 |
|
|
push_hi <= 'b1; // push
|
| 400 |
|
|
sub <= 'b1; // sub
|
| 401 |
|
|
ext <= 'b1; // extended
|
| 402 |
|
|
sgn <= 'b0; // unsigned
|
| 403 |
|
|
end
|
| 404 |
|
|
op_mul : begin
|
| 405 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 406 |
|
|
push_hi <= 'b1; // push
|
| 407 |
|
|
mul <= 'b1; // multiply
|
| 408 |
|
|
end
|
| 409 |
|
|
op_mul_x : begin
|
| 410 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 411 |
|
|
push_hi <= 'b1; // push
|
| 412 |
|
|
mul <= 'b1; // multiply
|
| 413 |
|
|
ext <= 'b1; // extended
|
| 414 |
|
|
end
|
| 415 |
|
|
op_mul_ux : begin
|
| 416 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 417 |
|
|
push_hi <= 'b1; // push
|
| 418 |
|
|
mul <= 'b1; // multiply
|
| 419 |
|
|
ext <= 'b1; // extended
|
| 420 |
|
|
sgn <= 'b0; // unsigned
|
| 421 |
|
|
end
|
| 422 |
|
|
op_shl : begin
|
| 423 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 424 |
|
|
push_hi <= 'b1; // push
|
| 425 |
|
|
shl <= 'b1; // shift left
|
| 426 |
|
|
end
|
| 427 |
|
|
op_shl_u : begin
|
| 428 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 429 |
|
|
push_hi <= 'b1; // push
|
| 430 |
|
|
shl <= 'b1; // shift left
|
| 431 |
|
|
sgn <= 'b0; // unsigned
|
| 432 |
|
|
end
|
| 433 |
|
|
/////////////
|
| 434 |
|
|
// group 2 //
|
| 435 |
|
|
/////////////
|
| 436 |
|
|
op_and : begin
|
| 437 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 438 |
|
|
push_hi <= 'b1; // push
|
| 439 |
|
|
end
|
| 440 |
|
|
op_or : begin
|
| 441 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 442 |
|
|
push_hi <= 'b1; // push
|
| 443 |
|
|
lg <= 'd1;
|
| 444 |
|
|
end
|
| 445 |
|
|
op_xor : begin
|
| 446 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 447 |
|
|
push_hi <= 'b1; // push
|
| 448 |
|
|
lg <= 'd2;
|
| 449 |
|
|
end
|
| 450 |
|
|
op_not : begin
|
| 451 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 452 |
|
|
push_hi <= 'b1; // push
|
| 453 |
|
|
lg <= 'd3;
|
| 454 |
|
|
end
|
| 455 |
|
|
op_and_b : begin
|
| 456 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 457 |
|
|
push_hi <= 'b1; // push
|
| 458 |
|
|
ext <= 'b1; // extended
|
| 459 |
|
|
end
|
| 460 |
|
|
op_or_b : begin
|
| 461 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 462 |
|
|
push_hi <= 'b1; // push
|
| 463 |
|
|
lg <= 'd1;
|
| 464 |
|
|
ext <= 'b1; // extended
|
| 465 |
|
|
end
|
| 466 |
|
|
op_xor_b : begin
|
| 467 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 468 |
|
|
push_hi <= 'b1; // push
|
| 469 |
|
|
lg <= 'd2;
|
| 470 |
|
|
ext <= 'b1; // extended
|
| 471 |
|
|
end
|
| 472 |
|
|
/////////////
|
| 473 |
|
|
// group 3 //
|
| 474 |
|
|
/////////////
|
| 475 |
|
|
op_lit : begin
|
| 476 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 477 |
|
|
push_hi <= 'b1; // push
|
| 478 |
|
|
lit <= 'b1; // lit
|
| 479 |
|
|
dm <= 'b1; // dm
|
| 480 |
|
|
end
|
| 481 |
|
|
op_lit_u : begin
|
| 482 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 483 |
|
|
push_hi <= 'b1; // push
|
| 484 |
|
|
lit <= 'b1; // lit
|
| 485 |
|
|
dm <= 'b1; // dm
|
| 486 |
|
|
sgn <= 'b0; // unsigned
|
| 487 |
|
|
end
|
| 488 |
|
|
op_lit_x : begin
|
| 489 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 490 |
|
|
push_hi <= 'b1; // push
|
| 491 |
|
|
lit <= 'b1; // lit
|
| 492 |
|
|
dm <= 'b1; // dm
|
| 493 |
|
|
ext <= 'b1; // extended
|
| 494 |
|
|
end
|
| 495 |
|
|
op_cpy : begin
|
| 496 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 497 |
|
|
push_hi <= 'b1; // push
|
| 498 |
|
|
cpy <= 'b1; // copy
|
| 499 |
|
|
end
|
| 500 |
|
|
op_pc : begin
|
| 501 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 502 |
|
|
push_hi <= 'b1; // push
|
| 503 |
|
|
rtn <= 'b1; // push pc
|
| 504 |
|
|
end
|
| 505 |
|
|
op_gsb : begin
|
| 506 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 507 |
|
|
push_hi <= 'b1; // push
|
| 508 |
|
|
gto <= 'b1; // goto
|
| 509 |
|
|
rtn <= 'b1; // push pc
|
| 510 |
|
|
end
|
| 511 |
|
|
op_cls : begin
|
| 512 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 513 |
|
|
stk_clr <= 'b1; // stack clear
|
| 514 |
|
|
a_pop <= 'b0; // no pop
|
| 515 |
|
|
b_pop <= 'b0; // no pop
|
| 516 |
|
|
end
|
| 517 |
|
|
op_pop : begin
|
| 518 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 519 |
|
|
end
|
| 520 |
|
|
op_nop : begin
|
| 521 |
|
|
op_code_ok_hi <= 'b1; // good opcode
|
| 522 |
|
|
a_pop <= 'b0; // no pop
|
| 523 |
|
|
b_pop <= 'b0; // no pop
|
| 524 |
|
|
end
|
| 525 |
|
|
default: begin
|
| 526 |
|
|
// nothing here
|
| 527 |
|
|
end
|
| 528 |
|
|
endcase
|
| 529 |
|
|
end
|
| 530 |
|
|
end
|
| 531 |
|
|
end
|
| 532 |
|
|
|
| 533 |
|
|
|
| 534 |
|
|
// decode test
|
| 535 |
|
|
always @ ( * ) begin
|
| 536 |
|
|
casex ( { tst_hi, tst_lo } )
|
| 537 |
|
|
2'b00 : { tst_gt, tst_lt, tst_eq } <= 3'b111; // default is always
|
| 538 |
|
|
2'b01 : { tst_gt, tst_lt, tst_eq } <= tst_lo_field;
|
| 539 |
|
|
2'b1x : { tst_gt, tst_lt, tst_eq } <= tst_hi_field;
|
| 540 |
|
|
endcase
|
| 541 |
|
|
end
|
| 542 |
|
|
|
| 543 |
|
|
// decode immediate data
|
| 544 |
|
|
always @ ( * ) begin
|
| 545 |
|
|
case ( imda_6b )
|
| 546 |
|
|
1'b0 : im_data <= im_field; // byte default
|
| 547 |
|
|
1'b1 : im_data <= $signed( im_field[5:0] ); // signed 6 bit
|
| 548 |
|
|
endcase
|
| 549 |
|
|
end
|
| 550 |
|
|
|
| 551 |
|
|
// assign immediate address
|
| 552 |
|
|
assign im_addr = im_field[4:0];
|
| 553 |
|
|
|
| 554 |
|
|
// decode control
|
| 555 |
|
|
assign imda = imda_8b | imda_6b;
|
| 556 |
|
|
assign imad = imad_5b;
|
| 557 |
|
|
|
| 558 |
|
|
// decode pop & push
|
| 559 |
|
|
assign pop = ( a_pop << a_sel ) | ( b_pop << b_sel );
|
| 560 |
|
|
assign push = ( ( push_lo | push_hi ) << a_sel );
|
| 561 |
|
|
|
| 562 |
|
|
// decode errors
|
| 563 |
|
|
assign op_code_er = ~( op_ok | op_code_ok_lo | op_code_ok_hi );
|
| 564 |
|
|
|
| 565 |
|
|
|
| 566 |
|
|
// optional output registers
|
| 567 |
|
|
vector_sr
|
| 568 |
|
|
#(
|
| 569 |
|
|
.REGS ( REGS_OUT ),
|
| 570 |
|
|
.DATA_W ( 1+IM_ADDR_W+IM_DATA_W+10+STACKS+STACKS+STK_W+STK_W+9+LG_W+4 ),
|
| 571 |
|
|
.RESET_VAL ( 0 )
|
| 572 |
|
|
)
|
| 573 |
|
|
out_regs
|
| 574 |
|
|
(
|
| 575 |
|
|
.clk_i ( clk_i ),
|
| 576 |
|
|
.rst_i ( rst_i ),
|
| 577 |
|
|
.data_i ( { op_code_er, im_addr, im_data, pc_clr, intr, gto, jmp, lit, tst_gt, tst_lt, tst_eq, tst_ab, stk_clr, pop, push, a_sel, b_sel, imda, imad, rtn, dm, cpy, shl, mul, sub, add, lg, ext, sgn, rd, wr } ),
|
| 578 |
|
|
.data_o ( { op_code_er_o, im_addr_o, im_data_o, pc_clr_o, intr_o, gto_o, jmp_o, lit_o, tst_gt_o, tst_lt_o, tst_eq_o, tst_ab_o, stk_clr_o, pop_o, push_o, a_sel_o, b_sel_o, imda_o, imad_o, rtn_o, dm_o, cpy_o, shl_o, mul_o, sub_o, add_o, lg_o, ext_o, sgn_o, rd_o, wr_o } )
|
| 579 |
|
|
);
|
| 580 |
|
|
|
| 581 |
|
|
|
| 582 |
|
|
endmodule
|
