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[/] [hive/] [trunk/] [v04.05/] [boot_code/] [boot_code_v_ints.h] - Blame information for rev 4

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Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : boot_code.h`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Boot code for a processor core.`
10
11			`Instantiates:`
12			`- Nothing.`
13
14			`Notes:`
15			`- For testing (@ core.v):`
16			`CLR_BASE = 'h0;`
17			`CLR_SPAN = 2; // gives 4 instructions`
18			`INTR_BASE = 'h20; // 'd32`
19			`INTR_SPAN = 2; // gives 4 instructions`
20
21
22			`--------------------------------------------------------------------------------`
23			`*/`
24
25			`/*`
26			`--------------------`
27			`-- external stuff --`
28			`--------------------`
29			`*/`
30			`include "op_encode.h"
31			`include "reg_set_addr.h"
32			`include "boot_code_defs.h"
33
34
35			`/*`
36			`----------------------------------------`
37			`-- initialize: fill with default data --`
38			`----------------------------------------`
39			`*/`
40			`integer i;`
41
42			`initial begin`
43
44			`/* // fill with nop (some compilers need this)`
45			`for ( i = 0; i < CAPACITY; i = i+1 ) begin`
46			ram[i] = { `nop, `__, `__ };
47			`end`
48			`*/`
49
50			`/*`
51			`---------------`
52			`-- boot code --`
53			`---------------`
54			`*/`
55
56
57			`// Thread 0 : enable interrupts`
58			`// All threads : output thread ID @ interrupt`
59
60			`///////////////`
61			`// clr space //`
62			`///////////////`
63
64			`// thread 0 : enable interrupts & loop forever`
65			i='h0; ram[i] = { `lit_u, `__, `s3 }; // s3='h0100
66			`i=i+1; ram[i] = 16'h0100 ; //`
67			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3
68			i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
69			`// all others : loop forever`
70			i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
71			i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
72			i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
73			i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
74			i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
75			i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
76			i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
77
78			`////////////////`
79			`// intr space //`
80			`////////////////`
81
82			`// all threads : read and output thread ID`
83			i='h20; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
84			`i=i+1; ram[i] = 16'h0110 ; //`
85			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
86			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
87			`//`
88			i='h24; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
89			`i=i+1; ram[i] = 16'h0110 ; //`
90			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
91			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
92			`//`
93			i='h28; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
94			`i=i+1; ram[i] = 16'h0110 ; //`
95			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
96			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
97			`//`
98			i='h2c; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
99			`i=i+1; ram[i] = 16'h0110 ; //`
100			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
101			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
102			`//`
103			i='h30; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
104			`i=i+1; ram[i] = 16'h0110 ; //`
105			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
106			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
107			`//`
108			i='h34; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
109			`i=i+1; ram[i] = 16'h0110 ; //`
110			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
111			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
112			`//`
113			i='h38; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
114			`i=i+1; ram[i] = 16'h0110 ; //`
115			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
116			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
117			`//`
118			i='h3c; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
119			`i=i+1; ram[i] = 16'h0110 ; //`
120			i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
121			i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
122
123
124
125			`///////////////////////`
126			`// code & data space //`
127			`///////////////////////`
128
129
130
131			`/////////////////`
132			`// subroutines //`
133			`/////////////////`
134
135
136			`// sub : enable all ints, return to (s3)`
137			i='h100; ram[i] = { `dat_is, `INTR_EN, `s1 }; // s1=reg addr
138			i=i+1; ram[i] = { `dat_is, -6'd1, `s0 }; // s0=-1
139			i=i+1; ram[i] = { `reg_w, `P1, `P0 }; // (s1)=s0, pop both
140			i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
141
142			`// sub : read thread ID & write to GPIO, return to (s3)`
143			i='h110; ram[i] = { `dat_is, `THRD_ID, `s1 }; // s1=reg addr
144			i=i+1; ram[i] = { `reg_rs, `P1, `s0 }; // s0=(s1), pop s1
145			i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
146			i=i+1; ram[i] = { `reg_w, `P1, `P0 }; // (s1)=s0, pop both
147			i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
148
149
150			`end`

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[/] [hive/] [trunk/] [v04.05/] [boot_code/] [boot_code_v_ints.h] - Blame information for rev 4